DSPIC33FJ32MC202-E/MM Microchip Technology, DSPIC33FJ32MC202-E/MM Datasheet - Page 311

• Manufacturer Part Number: DSPIC33FJ32MC202-E/MM
• Description: 16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32MC202-E/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision H (February 2011)
This revision includes typographical and formatting
changes throughout the data sheet text. In addition, all
instances of V
All other major changes are referenced by their
respective section in the following table.
TABLE A-6:
© 2011 Microchip Technology Inc.
High-Performance, 16-bit Digital Signal
Controllers
Section 2.0 “Guidelines for Getting Started
with 16-bit Digital Signal Controllers”
Section 3.0 “CPU”
Section 4.0 “Memory Organization”
Section 8.0 “Oscillator Configuration”
Section 20.0 “10-bit/12-bit Analog-to-Digital
Converter (ADC)”
Section 21.0 “Special Features”
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
DDCORE
Section Name
MAJOR SECTION UPDATES
have been removed.
Added the SSOP package information (see “Packaging:”,
and
Updated the title of
Connection
The frequency limitation for device PLL start-up conditions was
updated in
Start-up”.
The second paragraph in
Removed references to DMA in the CPU Core Block Diagram (see
Figure
Updated the data memory reference in the third paragraph in
Section 4.2 “Data Address
All Resets values for the following SFRs in the Timer Register Map
were changed (see
• TMR1
• TMR2
• TMR3
Added Note 3 to the OSCCON: Oscillator Control Register (see
Register
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register
Updated the V
(see
Added a new paragraph and removed the third paragraph in
Section 21.1 “Configuration
Added the column “RTSP Effects” to the Configuration Bits
Descriptions (see
“Pin
Figure 20-1
3-1).
8-1).
8-2).
8-3).
8-4).
Diagrams”).
Section 2.7 “Oscillator Value Conditions on Device
(Vcap)”.
REFL
and
Table
Section 2.3 “CPU Logic Filter Capacitor
references in the ADC1 module block diagrams
Table
Figure
Update Description
21-2).
Section 2.9 “Unused I/Os”
4-5):
20-2).
Space”.
Bits”.
DS70283H-page 311
was updated.
Table
1,