ISPGDX160A-5Q208 Lattice, ISPGDX160A-5Q208 Datasheet - Page 23

• Manufacturer Part Number: ISPGDX160A-5Q208
• Description: Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
• Manufacturer: Lattice

Specifications of ISPGDX160A-5Q208

• Mounting Style: Through Hole
• Number Of Arrays: 1
• Operating Supply Voltage: 5 V
• Supply Type: Single
• Configuration: 160 x 160
• Package / Case: DIP-24
• Input Level: TTL
• Output Level: TTL
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ispLEVER Development System supports ispGDX
design using a VHDL or Verilog language syntax. From
creation to in-system programming, the ispLEVER sys-
tem is an easy-to-use, self-contained design tool.
Features
All necessary programming of the ispGDXV/VA is done
via four TTL level logic interface signals. These four
Figure 9. ispJTAG Device Programming Interface
ispLEVER Development System
In-System Programmability
• VHDL and Verilog Synthesis Support Available
• ispGDX Design Compiler
• Industry Standard JEDEC File for Programming
• Min/Max Timing Report
• Interfaces To Popular Timing Simulators
• User Electronic Signature (UES) Support
• Detailed Log and Report Files For Easy Design
• On-line Help
• Windows
• Solaris
Debug
Windows NT
- Design Rule Checker
- I/O Connectivity Checker
- Automatic Compiler Function
TDO
TDI
®
TMS
and HP-UX Versions Available
®
TCK
XP, Windows 2000, Windows 98 and
EPEN
®
Compatible
160V/VA
ispGDX
Device
ispJTAG
Programming
Interface
Device
ispLSI
Specifications ispGDX160V/VA
22
ispMACH
signals are fed into the on-chip programming circuitry
where a state machine controls the programming.
On-chip programming can be accomplished using an
IEEE 1149.1 boundary scan protocol. The IEEE 1149.1-
compliant interface signals are Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS) control. The EPEN pin is also used to enable or
disable the JTAG port.
The embedded controller port enable pin (EPEN) is used
to enable the JTAG tap controller and in that regard has
similar functionality to a TRST pin. When the pin is driven
high, the JTAG TAP controller is enabled. This is also true
when the pin is left unconnected, in which case the pin is
pulled high by the permanent internal pullup. This allows
ISP programming and BSCAN testing to take place as
specified by the Instruction Table.
When the pin is driven low, the JTAG TAP controller is
driven to a reset state asynchronously. It stays there
while the pin is held low. After pulling the pin high the
JTAG controller becomes active. The intent of this fea-
ture is to allow the JTAG interface to be directly controlled
by the data bus of an embedded controller (hence the
name Embedded Port Enable). The EPEN signal is used
as a “device select” to prevent spurious programming
and/or testing from occuring due to random bit patterns
on the data bus. Figure 9 illustrates the block diagram for
the ispJTAG™ interface.
Device
160V/VA
ispGDX
Device
160V/VA
ispGDX
Device