ISPGDX160A-5Q208 Lattice, ISPGDX160A-5Q208 Datasheet - Page 30

• Manufacturer Part Number: ISPGDX160A-5Q208
• Description: Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
• Manufacturer: Lattice

Specifications of ISPGDX160A-5Q208

• Mounting Style: Through Hole
• Number Of Arrays: 1
• Operating Supply Voltage: 5 V
• Supply Type: Single
• Configuration: 160 x 160
• Package / Case: DIP-24
• Input Level: TTL
• Output Level: TTL
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal
I/O Locations: ispGDX160V/VA (Ordered by 208-Ball BGA Location)
I/O A3
I/O D39
I/O D36
I/O D33
I/O D30
I/O D27
I/O D23
I/O D17
I/O D13
I/O D9
I/O D6
I/O D3
I/O D1
I/O A1
I/O A0
I/O D38
I/O D34
I/O D32
I/O D29
I/O D25
I/O D21
I/O D18
I/O D15
I/O D11
I/O D8
I/O D5
I/O D2
I/O D0
I/O A4
I/O A2
I/O D37
I/O D35
I/O D31
I/O D28
I/O D24
I/O D20
I/O D19
I/O D14
I/O D10
I/O D7
I/O D4
I/O C39
I/O C36
I/O A7
I/O A6
I/O A5
I/O D26
I/O D22
I/O D16
I/O D12
I/O C38
I/O C37
I/O C35
I/O A10
I/O
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
Control
MUXsel2
MUXsel2
MUXsel1
MUXsel2
MUXsel2
MUXsel1
MUXsel2
MUXsel1
MUXsel1
MUXsel1
MUXsel2
MUXsel2
MUXsel1
MUXsel1
MUXsel2
MUXsel2
MUXsel2
MUXsel1
MUXsel1
MUXsel2
MUXsel2
MUXsel2
MUXsel1
MUXsel1
MUXsel1
MUXsel1
MUXsel2
MUXsel1
Signal
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
PQFP fpBGA BGA
208
208
205
201
198
194
189
175
171
165
162
158
155
207
202
200
197
191
187
176
173
167
164
161
157
154
206
203
199
196
190
186
177
172
166
163
160
152
149
192
188
174
169
151
150
147
10
13
5
3
2
7
4
9
8
208
A11
A12
A13
A14
A15
A16
B10
B11
B12
B13
B14
B15
B16
C10
C11
C12
C13
C14
C15
C16
D10
D11
D14
D15
D16
A2
A3
A4
A5
A6
B4
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
D3
D7
D8
A1
A7
B1
B2
B3
B5
E1
272
D12
A14
C15
C16
C17
C19
C12
B13
B15
A16
A17
B17
D18
B12
C13
D14
B16
A18
C20
D20
A13
C14
D19
E18
F18
E3
B3
A3
B5
A5
B7
D9
C1
E4
C4
A4
C6
B6
B8
B9
E1
D1
D5
C5
D7
C7
A8
A9
G4
C8
C9
G2
F2
F3
Signal
I/O A9
I/O A8
I/O C33
I/O C34
I/O C32
I/O A13
I/O A12
I/O A11
I/O C30
I/O C31
I/O C29
I/O A17
I/O A15
I/O A16
I/O A14
I/O C28
I/O C26
I/O C27
I/O C25
I/O A21
I/O A19
I/O A20
I/O A18
I/O C24
I/O C21
I/O C23
I/O C22
I/O A22
I/O A24
I/O A23
I/O A25
I/O C17
I/O C19
I/O C18
I/O C20
I/O A26
I/O A28
I/O A27
I/O A29
I/O C13
I/O C15
I/O C14
I/O C16
I/O A30
I/O A31
I/O A32
I/O C11
I/O C10
I/O C12
I/O A33
I/O A34
I/O A35
I/O C7
I/O
CLK/CLK_EN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
Control
MUXsel1
MUXsel2
MUXsel1
MUXsel2
MUXsel2
MUXsel1
MUXsel1
MUXsel2
MUXsel2
MUXsel1
MUXsel2
MUXsel1
MUXsel1
MUXsel2
MUXsel2
MUXsel1
MUXsel1
MUXsel2
MUXsel2
MUXsel1
MUXsel1
MUXsel2
MUXsel2
MUXsel1
MUXsel1
MUXsel2
MUXsel2
Signal
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
Specifications ispGDX160V/VA
29
PQFP fpBGA BGA
208
145
146
144
142
143
141
140
136
138
135
134
131
133
132
126
128
127
130
122
124
123
125
118
117
120
114
12
11
18
16
14
22
20
21
19
27
24
26
23
28
30
29
31
32
36
34
37
38
39
40
41
42
43
208
G13
G14
G15
G16
M14
E14
E15
E16
F14
F15
F16
H13
H14
H15
H16
K13
K14
K15
K16
J13
J14
J15
J16
L14
L15
L16
M1
M2
M3
E2
E3
G1
G2
G3
G4
H1
H2
H3
H4
K1
K2
K3
K4
F1
F2
F3
J1
J2
J3
J4
L1
L2
L3
272
G17
G18
G19
G20
M17
M19
M18
M20
E20
F19
F20
H19
K18
K17
K19
P20
P19
N19
R19
J17
J18
J19
J20
L19
L20
L18
G1
M2
M1
M3
M4
G3
F1
H2
K2
K1
K3
P1
N2
P2
R1
P3
R2
T1
P4
R3
J4
J2
J1
J3
L3
L2
L4
Signal
I/O C8
I/O C9
I/O A36
I/O A37
I/O A38
I/O B13
I/O B18
I/O B21
I/O B25
I/O C3
I/O C5
I/O C6
I/O A39
I/O B0
I/O B4
I/O B7
I/O B11
I/O B16
I/O B23
I/O B27
I/O B30
I/O B35
I/O C0
I/O C1
I/O C4
I/O B1
I/O B2
I/O B6
I/O B9
I/O B12
I/O B15
I/O B19
I/O B20
I/O B24
I/O B28
I/O B31
I/O B33
I/O B36
I/O B39
I/O C2
I/O B3
I/O B5
I/O B8
I/O B10
I/O B14
I/O B17
I/O B22
I/O B26
I/O B29
I/O B32
I/O B34
I/O B37
I/O B38
I/O
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
CLK/CLKEN
MUXsel1
MUXsel1
MUXsel2
MUXsel1
MUXsel2
MUXsel2
MUXsel2
MUXsel2
MUXsel2
MUXsel1
MUXsel2
MUXsel1
MUXsel1
MUXsel2
MUXsel2
MUXsel2
MUXsel2
MUXsel1
MUXsel2
MUXsel1
MUXsel1
MUXsel1
MUXsel1
MUXsel1
MUXsel1
Control
Signal
CLK
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
OE
PQFP fpBGA BGA
208
115
116
109
112
113
106
107
111
101
104
108
102
103
45
46
47
66
71
83
87
48
50
55
58
62
69
85
90
94
99
51
52
57
60
64
68
72
82
86
92
95
97
53
56
59
61
67
70
84
88
93
96
98
M15
M16
208
N10
N14
N15
N16
P10
P11
P12
P13
P14
P15
P16
R10
R11
R12
R13
R14
R15
R16
T10
T11
T12
T13
T14
T15
T16
N1
N2
N3
N6
N7
N9
P1
P2
P3
P4
P5
P6
R1
R2
R3
R4
R5
R6
R7
R9
T1
T2
T3
T4
T5
T6
W17
W12
W13
W15
W16
W18
272
R20
R18
U14
U16
U20
U12
P18
V12
V13
T18
P17
Y13
Y15
T17
V20
T20
V15
Y17
Y19
Y14
Y16
V16
V17
W5
W6
W4
W8
W9
U1
T3
U2
Y7
V9
V1
U3
Y3
Y8
V2
V5
V6
V7
V4
Y4
Y5
U7
V8
U9