LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 24

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MII SELECT - Used to select the network interface port. When set, the LAN91C110 will use its MII port and interface a
PHY device at the nibble rate. This bit must always be set for proper chip function.
NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not
ready for a transfer. When clear, negates ARDY for two to three clocks on any cycle to the LAN91C110.
FULL STEP - Reserved
AUI SELECT - This bit is a general purpose output port. Its value drives pin AUISEL and can be used as a general
purpose non-volatile configuration pin. Defaults low.
Reserved - Must be 0.
INT SEL1-0 - Used to select interrupt pin. The bits must remain 00 for the interrupt pin to be asserted for interrupt
indication. All other bit combinations are undefined.
BANK 1
This register holds the I/O address decode option chosen for the LAN91C110. Is not usually modified during run-time.
A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the IOBASE for the
LAN91C110‘s registers. The 64k I/O space is fully decoded by the LAN91C110 down to a 16 location space, therefore the
unspecified address lines A4, A10, A11 and A12 must be all zeros.
The I/O base decode defaults to 300h (namely, the high byte defaults to 18h).
Reserved - Must be 0.
SMSC LAN91C110 Rev. B
OFFSET
2
HIGH
BYTE
BYTE
LOW
BASE ADDRESS REGISTER
A15
0
0
NAME
A14
0
0
DATASHEET
A13
0
0
Reserved
Page 24
A9
1
0
READ/WRITE
TYPE
A8
1
0
A7
0
0
SYMBOL
BAR
A6
0
0
Revision 1.0 (11-04-08)
A5
0
1
1