LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 7

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3
SMSC LAN91C110 Rev. B
97-98, 119,
144 TQFP
89, 91-95,
115-112,
121-123,
118, 117
PIN NO.
110-100
125-128
138
135
129
120
131
132
134
88
Address
Address
Enable
Data Bus D[15:0]
Reset
Asynchro-
nous
Ready
Local
Device
nAddress
Strobe
Interrupt
nRead
Strobe
nWrite
Strobe
NAME
Description of Pin Functions
A[15:1]
AEN
nBE[1:0]
RESET
ARDY
nLDEV
nADS
INTR0
nRD
nWR
SYMBOL
BUFFER
DATASHEET
TYPE
OD16
I/O8
O16
O4
IS
IS
IS
IS
I
I
I
Page 7
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Input. Used by LAN91C110 for internal register
selection.
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
Input. Used during LAN91C110 register accesses
to determine the width of the access and the
register(s) being accessed.
Bidirectional. 16-bit data bus used to access the
LAN91C110’s internal registers. Data bus has
weak internal pullups. Supports direct connection
to the system bus without external buffering.
Input. This input is not considered active unless it
is active for at least 100ns to filter narrow glitches.
Open drain output. ARDY may be used when
interfacing asynchronous buses to extend
accesses. Its rising (access completion) edge is
controlled by the XTAL1 clock and, therefore,
asynchronous to the host CPU or bus clock.
Note: Asserted for 100 to 150ns for the
appropriate NO WAIT bit state in the Configuration
register. See the NO WAIT bit description for
complete information.
Output. Local Device. This active low output is
asserted when AEN is low and A4-A15 decode to
the LAN91C110 address programmed into the
high byte of the Base Address Register. nLDEV*
is a combinatorial decode of unlatched address
and AEN signals.
Input. Address strobe. For systems that require
address latching. The rising edge of nADS
indicates the latching moment of A[1:15] and AEN.
All LAN91C110 internal functions of A[1:15] and
AEN are latched.
Output. The interrupt output is enabled by
selecting the appropriate routing bits (INT SEL 1-
0) in the Configuration Register.
Input. Used in asynchronous bus interfaces.
Input. Used in asynchronous bus interfaces.
DESCRIPTION
Revision 1.0 (11-04-08)
Datasheet