LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 30

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BANK 2
POINTER REGISTER - The value of this register determines the address to be accessed within the transmit or receive
areas. It will auto-increment on accesses to the data register when AUTO INCR. is set. The increment is by one for every
byte access, by two for every word access, and by four for every double word access. When RCV is set the address
refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is clear the address refers to
the transmit area and uses the packet number at the Packet Number Register.
READ - Determines the type of access to follow. If the READ bit is high the operation intended is a read. If the READ bit is
low the operation is a write. Loading a new pointer value, with the READ bit high, generates a pre-fetch into the Data
Register for read purposes.
Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than the last pre-fetched).
This allows any interrupt routine that uses the pointer, to save it and restore it without affecting the process being
interrupted. The Pointer Register should not be loaded until the Data Register FIFO is empty. The NOT EMPTY bit of this
register can be read to determine if the FIFO is empty. On reads, if IOCHRDY is not connected to the host, the Data Register
(ARDY) should not be read before 370ns after the pointer was loaded to allow the Data Register FIFO to fill.
If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last.
Reserved – Must be 0.
NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that the FIFO is empty
before loading a new pointer value. This is a read only bit.
Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value.
BANK 2
SMSC LAN91C110 Rev. B
8 THROUGH Bh
OFFSET
X
X
BYTE
BYTE
HIGH
LOW
OFFSET
6
X
X
RCV
0
0
DATA REGISTER
POINTER REGISTER
AUTO
INCR.
X
X
0
0
NAME
NAME
READ
X
X
0
0
DATA HIGH
DATA LOW
DATASHEET
Reserved
Page 30
POINTER LOW
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
0
0
X
X
READ/WRITE
NOT EMPTY is a read
EMPTY
NOT
TYPE
READ/WRITE
0
0
X
X
only bit
TYPE
0
0
X
X
POINTER HIGH
SYMBOL
DATA
0
0
SYMBOL
X
X
PTR
Revision 1.0 (11-04-08)
0
0
Datasheet