LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 3

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table Of Contents
Chapter 1
Chapter 2
Chapter 3
Chapter 4
4.1
4.2
Chapter 5
5.1
5.2
5.3
5.4
5.5
5.6
Chapter 6
6.1
6.2
Chapter 7
Chapter 8
List of Figures
Figure 2.1 – Pin Configuration ...................................................................................................................... 6
Figure 3.1 - LAN91C110 Block Diagram..................................................................................................... 10
Figure 3.2 - LAN91C110 System Diagram ................................................................................................. 10
Figure 4.1 - LAN91C110 Internal Block Diagram with Data Path ............................................................... 14
Figure 5.1 – Data Packet Format................................................................................................................ 15
Figure 5.2 – Interrupt Structure................................................................................................................... 33
Figure 5.3 – Interrupt Service Routine ........................................................................................................ 41
Figure 5.4 - RX INTR .................................................................................................................................. 42
Figure 5.5 - TX INTR................................................................................................................................... 43
Figure 5.6 - TXEMPTY INTR (Assumes auto release option selected)...................................................... 44
Figure 5.7 - Drive Send and Allocate Routines........................................................................................... 45
Figure 5.8 – Interrupt Generation for Transmit, Receive, MMU.................................................................. 48
Figure 7.1 - Asynchronous Cycle - nADS=0 ............................................................................................... 51
Figure 7.2 - Asynchronous Cycle - USING nADS....................................................................................... 51
Figure 7.3 – Address Latching for All Modes .............................................................................................. 52
SMSC LAN91C110 Rev. B
4.1.1
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
Description of Blocks......................................................................................................................... 11
CSMA/CD Block ................................................................................................................................ 11
Packet Format in Buffer Memory ...................................................................................................... 15
Typical Flow of Events for Transmit (Auto Release = 0)................................................................... 37
Typical Flow of Events for Transmit (Auto Release = 1)................................................................... 38
Typical Flow of Events for Receive ................................................................................................... 40
Memory Partitioning .......................................................................................................................... 46
Interrupt Generation .......................................................................................................................... 46
Maximum Guaranteed Ratings* ........................................................................................................ 49
DC Electrical Characteristics............................................................................................................. 49
Clock Generator Block................................................................................................................ 11
DMA Block .................................................................................................................................. 11
Arbiter Block................................................................................................................................ 11
MMU Block.................................................................................................................................. 12
BIU Block .................................................................................................................................... 12
MAC-PHY Interface Block .......................................................................................................... 12
MII Management Interface Block ................................................................................................ 13
General Description............................................................................................................................5
Pin Configuration ...............................................................................................................................6
Description of Pin Functions..............................................................................................................7
Functional Description .....................................................................................................................11
Data Structures and Registers .........................................................................................................15
Operational Description...................................................................................................................49
Timing Diagrams ..............................................................................................................................51
Package Outline ................................................................................................................................56
DATASHEET
Page 3
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Revision 1.0 (11-04-08)
Datasheet