LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 27

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BANK2
This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three
command bits determine the command issued as described below:
COMMAND SET:
xyz
000
001
010
011
100
101
110
111
SMSC LAN91C110 Rev. B
1)
2)
3)
4)
5)
6)
0)
7)
BYTE
BYTE
HIGH
LOW
OFFSET
ALLOCATE MEMORY FOR TX - N2, N1, N0 defines the amount of memory requested as (value + 1) * 256
bytes. Namely N2, N1, N0 = 1 will request 2 * 256 = 512 bytes. A shift-based divide by 256 of the packet
length yields the appropriate value to be used as N2, N1, N0. Immediately generates a completion code at
the ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful completion. N2,
N1, N0 are ignored by the LAN91C110 but should be implemented in LAN91C110 software drivers for
LAN9000 compatibility.
RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts, resets packet
FIFO pointers.
REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has completed processing of present
receive frame. This command removes the receive packet number from the RX FIFO and brings the next
receive frame (if any) to the RX area (output of RX FIFO).
REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all memory used by the packet
presently at the RX FIFO output. The MMU busy time after issuing REMOVE and RELEASE command
depends on the time when the busy bit is cleared. The time from issuing REMOVE and RELEASE command
on the last receive packet to the time when receive FIFO is empty depends on RX INT bit turning low. An
alternate approach can be checking the read RX FIFO register.
RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the PACKET NUMBER
REGISTER. Should not be used for frames pending transmission. Typically used to remove transmitted
frames, after reading their completion status. Can be used following 3) to release receive packet memory in
a more flexible way than 4).
loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER.
RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO holding the packet numbers
awaiting transmission and the TX Completion FIFO. This command provides a mechanism for canceling
packet transmissions, and reordering or bypassing the transmit queue. The RESET TX FIFOs command
should only be used when the transmitter is disabled. Unlike the RESET MMU command, the RESET TX
FIFOs does not release any memory.
NOOP - NO OPERATION
ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just
0
X
COMMAND
MMU COMMAND REGISTER
Y
NAME
Z
DATASHEET
Reserved
Page 27
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
BUSY Bit Readable
Reserved
WRITE ONLY
TYPE
N2
N1
SYMBOL
MMUCR
Revision 1.0 (11-04-08)
N0/BUSY
0
Datasheet