LAN8187-JT SMSC, LAN8187-JT Datasheet - Page 78

• Manufacturer Part Number: LAN8187-JT
• Description: Ethernet ICs HiPerfrm Ethrnt PHY
• Manufacturer: SMSC
• Type: MII/RMII Ethernet Transceiverr

Specifications of LAN8187-JT

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 802.3ab
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Supply Current (max): 39 mA, 81.6 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 Revision History
Revision 1.7 (03-04-11)
Rev. 1.7 (03-04-11)
Rev. 1.6 (02-27-09)
REVISION LEVEL & DATE
Table 6.1, “SMI Timing
Values,” on page 57
Table 6.11, “Reset Timing
Values,” on page 66
Table 7.5, “MII Bus Interface
Signals,” on page
Table 7.7, “LED Signals,” on
page
“Configuration Inputs,” on
page
“General Signals,” on
page 73
Table 5.39, “Register 18 -
Special Modes,” on page 46
Section 4.6.3, "MII vs. RMII
Configuration," on page 26
Section 5.4.8.2, "Far
Loopback," on page 54
Section 4.6.3
Table 6.11
Section 6.6
Section 6.3
Section 5.4.6
Table 5.34
Section 5.4.8
Section 4.6.3
Section 4.6.2.1
SECTION/FIGURE/ENTRY
Table 10.1 Customer Revision History
72,
72,
Table 7.8,
Table 7.9,
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
DATASHEET
71,
78
Corrected T1.2 maximum value to 300ns.
Corrected T11.4 minimum value to 3ns.
Corrected T11.3 to 2ns.
Corrected VIH and VIL values to 0.68*VDDIO and
0.4*VDDIO, respectively.
Updated section to remove information about
register control of the MII/RMII mode.
Updated section to remove information about
register control of the MII/RMII mode.
Revised the first two paragraphs in
"MII vs. RMII Configuration," on page
Changed the MIN value for T11.3:
From: “400”
To: “10”
Added section on clock, with crystal specification
table.
Improved timing values.
Removed reference to internal POR system. Added
note that the nRST should be low until VDDIO and
VDD_CORE are stable. Added Figure.
Corrected bit value for Asymmetric and Symmetric
PAUSE.
Enhanced this section.
Added information about register bit 18.14.
First sentence of second paragraph changed:
From: “between 35% and 65%”
To: “between 40% and 60%“
Corrected errrant bit 15 description (reserved).
Updated MIIMODE bit description and added
Added note regarding default MIIMODE value.
note: “When writing to this register, the default
value of this bit must always be written back.”
CORRECTION
SMSC LAN8187/LAN8187i
Section 4.6.3,
26.
Datasheet
®
Technology