HUF76609D3ST Fairchild Semiconductor, HUF76609D3ST Datasheet

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HUF76609D3ST

Manufacturer Part Number
HUF76609D3ST
Description
MOSFET N-CH 100V 10A DPAK
Manufacturer
Fairchild Semiconductor
Series
UltraFET™r
Datasheet

Specifications of HUF76609D3ST

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
160 mOhm @ 10A, 10V
Drain To Source Voltage (vdss)
100V
Current - Continuous Drain (id) @ 25° C
10A
Vgs(th) (max) @ Id
3V @ 250µA
Gate Charge (qg) @ Vgs
16nC @ 10V
Input Capacitance (ciss) @ Vds
425pF @ 25V
Power - Max
49W
Mounting Type
Surface Mount
Package / Case
DPak, TO-252 (2 leads+tab), SC-63
Configuration
Single
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
0.13 Ohms
Drain-source Breakdown Voltage
100 V
Gate-source Breakdown Voltage
+/- 16 V
Continuous Drain Current
10 A
Power Dissipation
49 W
Maximum Operating Temperature
+ 175 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HUF76609D3ST
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
©2001 Fairchild Semiconductor Corporation
10A, 100V, 0.165 Ohm, N-Channel, Logic
Level UltraFET® Power MOSFET
Packaging
Symbol
Absolute Maximum Ratings
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (R
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain Current
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Maximum Temperature for Soldering
NOTE:
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
1. T
Continuous (T
Continuous (T
Continuous (T
Continuous (T
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Derate Above 25
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
(FLANGE)
DRAIN
J
= 25
JEDEC TO-251AA
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
HUF76609D3
o
C to 150
C
C
C
C
= 25
= 25
= 100
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
o
C.
o
o
C, V
C, V
o
o
GS
G
C, V
C, V
SOURCE
DRAIN
= 20k ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
GS
GATE
GS
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
S
T
SOURCE
Data Sheet
GATE
For severe environments, see our Automotive HUFA series.
C
= 25
JEDEC TO-252AA
HUF76609D3S
o
C, Unless Otherwise Specified
(FLANGE)
DRAIN
Features
• Ultra Low On-Resistance
• Simulation Models
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Switching Time vs R
Ordering Information
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76609D3ST.
HUF76609D3
HUF76609D3S
- r
- r
- Temperature Compensated PSPICE® and SABER™
- Spice and SABER Thermal Impedance Models
- www.Fairchildsemi.com
PART NUMBER
HUF76609D3, HUF76609D3S
Electrical Models
DS(ON)
DS(ON)
December 2001
J
, T
DGR
DSS
STG
DM
pkg
GS
= 0.160
= 0.165
D
D
D
D
D
L
HUF76609D3, HUF76609D3S
TO-251AA
TO-252AA
GS
V
V
PACKAGE
GS
GS
Figures 6, 17, 18
Curves
-55 to 175
Figure 4
0.327
10V
5V
100
100
300
260
10
10
49
16
7
7
HUF76609D3, HUF76609D3S Rev. B
76609D
76609D
BRAND
UNITS
W/
o
o
o
W
V
V
V
A
A
A
A
C
C
C
o
C

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HUF76609D3ST Summary of contents

Page 1

... Peak Current vs Pulse Width Curve • UIS Rating Curve • Switching Time vs R Ordering Information PART NUMBER HUF76609D3 HUF76609D3S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF76609D3ST Unless Otherwise Specified = 0.160 10V 0.165 ...

Page 2

... Gate to Drain “Miller” Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ©2001 Fairchild Semiconductor Corporation o C, Unless Otherwise Specified SYMBOL TEST CONDITIONS 250 (Figure 12) DSS ...

Page 3

... SINGLE PULSE 0. FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 200 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION ©2001 Fairchild Semiconductor Corporation 150 175 125 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT RECTANGULAR PULSE DURATION ( PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY V ...

Page 4

... D 140 120 100 GATE TO SOURCE VOLTAGE (V) GS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT ©2001 Fairchild Semiconductor Corporation (Continued) 100 s 1ms 10ms o C 100 300 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING o C 3.0 3 ...

Page 5

... DRAIN TO SOURCE VOLTAGE (V) DS FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 4.5V 50V d(OFF GATE TO SOURCE RESISTANCE ( ) GS FIGURE 15. SWITCHING TIME vs GATE RESISTANCE ©2001 Fairchild Semiconductor Corporation (Continued 250 120 160 200 o C) FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN ISS OSS RSS ...

Page 6

... Test Circuits and Waveforms VARY t TO OBTAIN P R REQUIRED PEAK FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT g(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 21. SWITCHING TIME TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation DUT 0. DUT g(REF DUT DSS FIGURE 18. UNCLAMPED ENERGY WAVEFORMS Q g(TOT) ...

Page 7

... S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.3) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2001 Fairchild Semiconductor Corporation DPLCAP 10 RSLC2 ...

Page 8

... Fairchild Semiconductor Corporation DPLCAP 10 RSLC2 - 6 ESG 8 EVTHRES + ...

Page 9

... Fairchild Semiconductor Corporation JUNCTION th RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 ...

Page 10

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FAST Bottomless™ FASTr™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DenseTrench™ ...

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