FQD12N20LTM Fairchild Semiconductor, FQD12N20LTM Datasheet - Page 5

MOSFET N-CH 200V 9A DPAK

FQD12N20LTM

Manufacturer Part Number
FQD12N20LTM
Description
MOSFET N-CH 200V 9A DPAK
Manufacturer
Fairchild Semiconductor
Series
QFET™r
Datasheets

Specifications of FQD12N20LTM

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
280 mOhm @ 4.5A, 10V
Drain To Source Voltage (vdss)
200V
Current - Continuous Drain (id) @ 25° C
9A
Vgs(th) (max) @ Id
2V @ 250µA
Gate Charge (qg) @ Vgs
21nC @ 5V
Input Capacitance (ciss) @ Vds
1080pF @ 25V
Power - Max
2.5W
Mounting Type
Surface Mount
Package / Case
DPak, TO-252 (2 leads+tab), SC-63
Configuration
Single
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
0.28 Ohm @ 10 V
Forward Transconductance Gfs (max / Min)
11.6 S
Drain-source Breakdown Voltage
200 V
Gate-source Breakdown Voltage
+/- 20 V
Continuous Drain Current
9 A
Power Dissipation
2500 mW
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
FQD12N20LTM
FQD12N20LTMTR

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Part Number
Manufacturer
Quantity
Price
Part Number:
FQD12N20LTM
Manufacturer:
FAIRCHILD
Quantity:
6 000
Part Number:
FQD12N20LTM
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Company:
Part Number:
FQD12N20LTM
Quantity:
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©2009 Fairchild Semiconductor Corporation
10V
10V
12V
12V
5V
5V
t
t
p
p
3mA
3mA
200nF
200nF
R
R
R
R
G
G
G
G
50KΩ
50KΩ
V
V
V
V
GS
GS
GS
GS
Unclamped Inductive Switching Test Circuit & Waveforms
V
V
V
V
300nF
300nF
I
I
I
DS
DS
DS
DS
D
D
D
Resistive Switching Test Circuit & Waveforms
Gate Charge Test Circuit & Waveform
DUT
DUT
DUT
DUT
DUT
DUT
Same Type
Same Type
R
R
as DUT
as DUT
L
L L
L
L
V
V
DD
DD
V
V
DD
DD
V
V
DS
DS
BV
BV
V
V
V
V
5V
5V
V
V
V
V
DSS
DSS
I
I
DD
DD
AS
AS
GS
GS
DS
DS
GS
GS
E
E
E
10%
10%
AS
AS
AS
90%
90%
Q
Q
=
=
=
t
t
d(on)
d(on)
gs
gs
----
----
----
----
1
1
1
1
2
2
2
2
t
t
on
on
L I
L I
L I
t
t
r
r
I
I
AS
AS
AS
D
D
(t)
(t)
t
t
2
2
2
Q
Q
p
p
Q
Q
g
g
--------------------
--------------------
gd
gd
Charge
Charge
BV
BV
BV
BV
DSS
DSS
DSS
DSS
- V
- V
t
t
d(off)
d(off)
DD
DD
t
t
off
off
Time
Time
t
t
f
f
Rev. A2, January 2009
V
V
DS
DS
(t)
(t)

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