HUF75639S3ST Fairchild Semiconductor, HUF75639S3ST Datasheet
HUF75639S3ST
Specifications of HUF75639S3ST
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HUF75639S3ST Summary of contents
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... TO-247 HUF75639P3 TO-220AB HUF75639S3S TO-263AB HUF75639S3 TO-262AA NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF75639S3ST. Packaging JEDEC STYLE TO-247 DRAIN (TAB) JEDEC TO-263AB GATE SOURCE Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series ...
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... Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain “Miller” Charge ©2001 Fairchild Semiconductor Corporation Unless Otherwise Specified Unless Otherwise Specified SYMBOL TEST CONDITIONS ...
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... FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 2 DUTY CYCLE - DESCENDING ORDER 0.5 1 0.2 0.1 0.05 0.02 0.01 0.1 SINGLE PULSE 0. FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE ©2001 Fairchild Semiconductor Corporation o C, Unless Otherwise Specified SYMBOL TEST CONDITIONS 25V 0V, ISS 1MHz C OSS (Figure 12) C RSS SYMBOL ...
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... FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 100 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX DRAIN TO SOURCE VOLTAGE (V) DS FIGURE 7. SATURATION CHARACTERISTICS ©2001 Fairchild Semiconductor Corporation (Continued PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 300 T = MAX RATED 100 100 s 1ms 10ms = 100V 100 200 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322 ...
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... T , JUNCTION TEMPERATURE ( J FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT ©2001 Fairchild Semiconductor Corporation (Continued) 1.2 1.0 0.8 0.6 120 160 200 o C) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs ...
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... Test Circuits and Waveforms VARY t TO OBTAIN P R REQUIRED PEAK FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT G(REF) FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 18. SWITCHING TIME TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation DUT 0. DUT g(REF DUT DSS FIGURE 15. UNCLAMPED ENERGY WAVEFORMS Q g(TOT) ...
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... S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.95 VOFF = -2.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2001 Fairchild Semiconductor Corporation DPLCAP 5 10 ...
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... Fairchild Semiconductor Corporation DPLCAP 10 RSLC2 - 6 ESG 8 EVTHRES + ...
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... Fairchild Semiconductor Corporation JUNCTION TH RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 ...
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... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FAST Bottomless™ FASTr™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DenseTrench™ ...