MT47H64M8CF-25E IT:G Micron Technology Inc, MT47H64M8CF-25E IT:G Datasheet - Page 56

• Manufacturer Part Number: MT47H64M8CF-25E IT:G
• Description: 64MX8 DDR2 SDRAM PLASTIC IND TEMP FBGA 1.8V
• Manufacturer: Micron Technology Inc

Table 28: AC Input Test Conditions (Continued)
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
Parameter
Input hold timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
Input timing measurement reference level (single-ended)
DQS for x4, x8; UDQS, LDQS for x16
Input timing measurement reference level (differential)
CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,
RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16
Notes:
1. All voltages referenced to V
2. Input waveform setup timing (
3. See Input Slew Rate Derating (page 57).
4. The slew rate for single-ended inputs is measured from DC level to AC level, V
5. Input waveform hold (
6. Input waveform setup timing (
7. Input waveform setup timing (
8. Input waveform timing is referenced to the crossing point level (V
9. The slew rate for differentially ended inputs is measured from twice the DC level to
V
test, as shown in Figure 30 (page 68).
V
to V
Figure 23 (page 60), Figure 25 (page 61), Figure 27 (page 66), and Figure 29
(page 67).
V
test, as shown in Figure 30 (page 68).
referenced from the crossing of DQS, UDQS, or LDQS through the Vref level applied to
the device under test, as shown in Figure 32 (page 69).
is enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/
LDQS#, as shown in Figure 31 (page 68).
(V
is the complementary input signal, as shown in Figure 33 (page 69).
twice the AC level: 2 × V
V
rising edge and would be 250mV to –500mV for CK falling edge.
IH(AC)
IH(AC)
IL(DC)
IH(DC)
TR
REF
and V
level for a rising signal and V
level for a rising signal and V
on the rising edge and V
, the valid intersection is where the “tangent” line intersects V
on the falling edge. For example, the CK/CK# would be –250mV to 500mV for CK
CP
) applied to the device under test, where V
t
IH
IL(DC)
b
56
Symbol
) timing is referenced from the input signal crossing at the
V
SS
REF(DC)
V
V
to 2 × V
.
AC Overshoot/Undershoot Specification
RH
RD
t
t
t
IS
DS) and hold timing (
DS) and hold timing (
IL(AC)
b
) is referenced from the input signal crossing at the
IH(DC)
IL(AC)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
to V
IH(AC)
V
DDQ
512Mb: x4, x8, x16 DDR2 SDRAM
IH(DC)
for a falling signal applied to the device under
for a falling signal applied to the device under
Min
on the rising edge and 2 × V
× 0.49 V
See Note 5
on the falling edge. For signals referenced
V
IX(AC)
DDQ
t
t
DH) for single-ended data strobe is
DH) when differential data strobe
Max
TR
× 0.51
is the true input signal and V
2004 Micron Technology, Inc. All rights reserved.
IX
Units
) of two input signals
V
V
REF
IL(AC)
, as shown in
to 2 ×
1, 3, 7, 8, 9
IL(DC)
1, 3, 4, 5
1, 3, 4, 6
Notes
to
CP