MT47H64M8CF-25E IT:G Micron Technology Inc, MT47H64M8CF-25E IT:G Datasheet - Page 81

• Manufacturer Part Number: MT47H64M8CF-25E IT:G
• Description: 64MX8 DDR2 SDRAM PLASTIC IND TEMP FBGA 1.8V
• Manufacturer: Micron Technology Inc

Extended Mode Register (EMR)
Figure 36: EMR Definition
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
Notes:
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, on-
die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#
enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func-
tions are controlled via the bits shown in Figure 36. The EMR is programmed via the LM
command and will retain the stored information until it is programmed again or the de-
vice loses power. Reprogramming the EMR will not alter the contents of the memory ar-
ray, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time
tion. Violating either of these requirements could result in an unspecified operation.
BA2
E15
16
0
0
0
1
1
1. E16 (BA2) is only applicable for densities ≥1Gb, reserved for future use, and must be pro-
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-
3. Not all listed AL options are supported in any individual speed grade.
4. As detailed in the Initialization section notes, during initialization of the OCD operation,
1
E14
BA1
15
MRS
0
1
0
1
E12
grammed to 0.
served for future use and must be programmed to 0.
all three bits must be set to 1 for the OCD default state, then set to 0 before initializa-
tion is finished.
0
1
14
BA0
E9
0
0
0
1
1
Extended mode register (EMR2)
Extended mode register (EMR3)
E11
Extended mode register (EMR)
0
1
Disabled
Outputs
Enabled
0
E8
n
An
RDQS Enable
0
0
1
0
1
E10
0
1
Mode register (MR)
Out
Mode Register Set
2
E7
12
Yes
0
1
0
0
1
A12
No
DQS# Enable
RDQS
Disable
Enable
OCD Operation
OCD exit
Reserved
Reserved
Reserved
Enable OCD defaults
11
DQS#
10
A10
OCD Program
9
A9
E6
0
0
1
1
4
8
A8
E2
0
1
0
1
7
A7 A6 A5 A4 A3
R
R
TT
R
TT
TT
6
(Nominal)
150
disabled
75
50
Posted CAS# R
5
81
E5
0
0
0
0
1
1
1
1
4
E4
0
0
1
1
0
0
1
1
3
E3
0
1
0
1
0
1
0
1
TT
2
A2 A1 A0
Posted CAS# Additive Latency (AL)
ODS
E1
0
1
t
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
MRD before initiating any subsequent opera-
DLL
E0
0
1
Output Drive Strength
0
512Mb: x4, x8, x16 DDR2 SDRAM
Disable (test/debug)
Reserved
Enable (normal)
Extended Mode Register (EMR)
Address bus
Extended mode
register (Ex)
Reduced
DLL Enable
Full
0
1
2
3
4
5
6
3
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