MT47H64M8CF-25E IT:G Micron Technology Inc, MT47H64M8CF-25E IT:G Datasheet - Page 89
MT47H64M8CF-25E IT:G
Manufacturer Part Number
MT47H64M8CF-25E IT:G
Description
64MX8 DDR2 SDRAM PLASTIC IND TEMP FBGA 1.8V
Manufacturer
Micron Technology Inc
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512MbDDR2.pdf - Rev. T 2/12 EN
10. Issue two or more REFRESH commands.
11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation
12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8,
13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and
14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles af-
15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configura-
16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are
(that is, to program operating parameters without resetting the DLL). To access the MR,
set BA0 and BA1 LOW; remaining MR bits must be set to desired settings. Mode Register
(MR) (page 76) for all MR requirements.
and E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0
HIGH and BA1 LOW (see Extended Mode Register (EMR) (page 81) for all EMR require-
ments.
E9 to “0,” and then setting all other desired parameters. To access the extended mode
registers, EMR, set BA0 HIGH and BA1 LOW for all EMR requirements.
ter the DLL RESET at Tf0.
tion; DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the ap-
propriate configuration (x4, x8, x16); DQ represents DQ[3:0] for x4, DQ[7:0] for x8 and
DQ[15:0] for x16.
required to be decoded).
89
Micron Technology, Inc. reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
2004 Micron Technology, Inc. All rights reserved.
Initialization
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