MT47H64M8CF-25E IT:G Micron Technology Inc, MT47H64M8CF-25E IT:G Datasheet - Page 72

• Manufacturer Part Number: MT47H64M8CF-25E IT:G
• Description: 64MX8 DDR2 SDRAM PLASTIC IND TEMP FBGA 1.8V
• Manufacturer: Micron Technology Inc

PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
10. A WRITE command may be applied after the completion of the READ burst.
5. The following states must not be interrupted by any executable command (DESELECT or
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and bursts are not in progress.
8. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
9. May or may not be bank-specific; if multiple banks are to be precharged, each must be
NOP commands must be applied on each positive clock edge during these states):
auto precharge enabled and READs or WRITEs with auto precharge disabled.
in a valid state for precharging.
Precharge:
Read with auto
precharge
enabled:
Row activate:
Write with auto
precharge
enabled:
Refresh:
Accessing
mode
register:
Precharge
all:
Starts with registration of a REFRESH command and ends when
met. After
state.
Starts with registration of the LOAD MODE command and ends when
t
all banks idle state.
Starts with registration of a PRECHARGE ALL command and ends when
t
MRD has been met. After
RP is met. After
Starts with registration of a PRECHARGE command and ends when
t
Starts with registration of a READ command with auto precharge
enabled and ends when
bank will be in the idle state.
Starts with registration of an ACTIVATE command and ends when
t
state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
bank will be in the idle state.
RP is met. After
RCD is met. After
72
t
RFC is met, the DDR2 SDRAM will be in the all banks idle
t
RP is met, all banks will be in the idle state.
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
RP is met, the bank will be in the idle state.
t
RCD is met, the bank will be in the row active
512Mb: x4, x8, x16 DDR2 SDRAM
t
MRD is met, the DDR2 SDRAM will be in the
t
t
RP has been met. After
RP has been met. After
2004 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the
RP is met, the
Commands
t
RFC is