MT48H8M32LFB5-75 IT:H Micron Technology Inc, MT48H8M32LFB5-75 IT:H Datasheet - Page 13

• Manufacturer Part Number: MT48H8M32LFB5-75 IT:H
• Description: DRAM Chip Mobile SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-75 IT:H

• Density: 256 Mb
• Maximum Clock Rate: 133 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 8|6 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Address Bus: 14b
• Access Time (max): 8/6ns
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Definition
Mode Register
Burst Length (BL)
Burst Type
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
There are two mode registers in the component: mode register and extended mode reg-
ister (EMR). The mode register is illustrated in Figure 6 on page 14. The mode register is
used to define the specific mode of operation of the SDRAM. This definition includes the
selection of a burst length (BL), a burst type, a CAS latency (CL), an operating mode and
a write burst mode, as shown in Figure 6 on page 14. The mode register is programmed
via the LMR command and will retain the stored information until it is programmed
again or the device loses power.
Mode register bits M[2:0] specify the BL, M3 specifies the type of burst, M[6:4] specify
the CL, M[8:7] specify the operating mode, M9 specifies the write burst mode, and
M[11:10] should be set to zero.
The mode register must be loaded when all banks are idle, and the controller must wait
t
will result in unspecified operation.
Read and write accesses to the SDRAM are burst oriented, with the BL being program-
mable, as shown in Figure 6 on page 14. The BL determines the maximum number of
column locations that can be accessed for a given READ or WRITE command. BL = 1, 2,
4, 8 locations are available for both the sequential and the interleaved burst types, and a
continuous page burst is available for the sequential type. The continuous page burst is
used in conjunction with the BURST TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the BL is effec-
tively selected. All accesses for that burst take place within this block, meaning that the
burst will wrap within the block if a boundary is reached. The block is uniquely selected
by A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8. The remaining (least
significant) address bit(s) is (are) used to select the starting location within the block.
Continuous page bursts wrap within the page if the boundary is reached.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the BL, the burst type, and the
starting column address, as shown in Table 4 on page 15.
MRD before initiating the subsequent operation. Violating either of these requirements
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile SDRAM
©2006 Micron Technology, Inc. All rights reserved.
Register Definition