MT48H8M32LFB5-75 IT:H Micron Technology Inc, MT48H8M32LFB5-75 IT:H Datasheet - Page 31

• Manufacturer Part Number: MT48H8M32LFB5-75 IT:H
• Description: DRAM Chip Mobile SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-75 IT:H

• Density: 256 Mb
• Maximum Clock Rate: 133 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 8|6 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Address Bus: 14b
• Access Time (max): 8/6ns
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 19:
Figure 20:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
WRITE Burst
WRITE-to-WRITE
Note:
Note:
COMMAND
COMMAND
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 21 on page 32. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRE-
CHARGE command to the same bank (provided that auto precharge was not activated),
and a continuous page WRITE burst can be truncated with a PRECHARGE command to
the same bank. The PRECHARGE command should be issued
which the last desired input data element is registered. The auto precharge mode
requires a
quency.
In addition, when truncating a WRITE burst, the DQM signal must be used to mask
input data for the clock edge prior to, and the clock edge coincident with, the PRE-
CHARGE command. An example is shown in Figure 21 on page 32. Data n + 1 is either
the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until
ADDRESS
ADDRESS
BL = 2. DQM is LOW.
BL = 2. DQM is LOW. Each WRITE command may be to any bank.
CLK
CLK
DQ
DQ
t
WR of at least one clock plus time (see note 24 on page 53), regardless of fre-
WRITE
BANK,
COL n
WRITE
BANK,
COL n
T0
D
D
T0
n
n
IN
IN
NOP
n + 1
T1
n + 1
NOP
D
T1
D
IN
IN
DON’T CARE
NOP
WRITE
T2
BANK,
COL b
T2
D
b
IN
31
DON’T CARE
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile SDRAM
t
WR after the clock edge at
©2006 Micron Technology, Inc. All rights reserved.
Operations
t
RP is met.