MT48H8M32LFB5-75 IT:H Micron Technology Inc, MT48H8M32LFB5-75 IT:H Datasheet - Page 17

• Manufacturer Part Number: MT48H8M32LFB5-75 IT:H
• Description: DRAM Chip Mobile SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-75 IT:H

• Density: 256 Mb
• Maximum Clock Rate: 133 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 8|6 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Address Bus: 14b
• Access Time (max): 8/6ns
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8:
Temperature-Compensated Self Refresh (TCSR)
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
EMR Definition
Notes: 1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
The EMR must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating any subsequent operation. Vio-
lating either of these requirements results in unspecified operation. Once the values are
entered, the EMR settings will be retained even after exiting deep power-down mode.
On this version of the Mobile SDR SDRAM, a temperature sensor is implemented for
automatic control of the self refresh oscillator on the device. Therefore, it is recom-
mended not to program or use the temperature-compensated self refresh control bits in
the extended mode register.
Programming of the TCSR bits has no effect on the device. The self refresh oscillator will
continue refresh at the factory programmed optimal rate for the device temperature.
E14
E12
0
–
0
0
1
1
E11
E13
0
–
0
1
0
1
E10
Mode Register Definintion
Standard mode register
Reserved
Extended mode register
Reserved
0
–
E9
0
–
14
BA1
E14
1
E8
0
–
0
BA0 A12
E13
13
E7
0
–
12
E12
E6–E0
Valid
–
11
A11
E11
set to “0”
10
A10
E10
Normal operation
All other states reserved
17
A9
E9
9
E6
0
0
1
1
A8
E8
8
E5
0
1
0
1
A7
E7
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A6
E6
6
DS
5
A5
E5
TCSR
256Mb: x16, x32 Mobile SDRAM
4
A4
E4
E2
0
0
0
0
1
1
1
1
1
A3
E3
3
E1
0
0
1
1
0
0
1
1
2
A2
E2
E0
0
1
0
1
0
1
0
1
PASR
A1
1
E1
Partial Array Self Refresh Coverage
Full array
Half array
Quarter array
Reserved
Reserved
One-eighth array
One-sixteenth array
Reserved
A0
0
E0
©2006 Micron Technology, Inc. All rights reserved.
Register Definition
Address Bus
Extended Mode
Register