MT48LC64M8A2TG-75 IT:C Micron Technology Inc, MT48LC64M8A2TG-75 IT:C Datasheet - Page 34

• Manufacturer Part Number: MT48LC64M8A2TG-75 IT:C
• Description: DRAM Chip SDRAM 512M-Bit 64Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC64M8A2TG-75 IT:C

• Package: 54TSOP-II
• Density: 512 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 26:
Figure 27:
Burst READ/Single WRITE
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
CLOCK SUSPEND During WRITE Burst
CLOCK SUSPEND During READ Burst
Note:
Note:
COMMAND
COMMAND
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
INTERNAL
INTERNAL
ADDRESS
ADDRESS
CLOCK
CLOCK
BL = 4 or greater. DM is LOW.
CL = 2, BL = 4 or greater. DQM is LOW.
CKE
CKE
CLK
CLK
DQ
D
IN
T0
NOP
BANK,
READ
COL n
T0
BANK,
WRITE
COL n
T1
D
T1
NOP
n
IN
T2
NOP
T2
34
D
OUT
Transitioning Data
n
T3
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Transitioning Data
n + 1
D
OUT
T4
NOP
n + 1
NOP
T4
D
IN
Don’t Care
T5
NOP
n + 2
T5
NOP
D
512Mb: x4, x8, x16 SDRAM
IN
n + 2
D
OUT
Don’t Care
T6
NOP
D
n + 3
©2000 Micron Technology, Inc. All rights reserved.
OUT
Operations