MT48LC64M8A2TG-75 IT:C Micron Technology Inc, MT48LC64M8A2TG-75 IT:C Datasheet - Page 37

• Manufacturer Part Number: MT48LC64M8A2TG-75 IT:C
• Description: DRAM Chip SDRAM 512M-Bit 64Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC64M8A2TG-75 IT:C

• Package: 54TSOP-II
• Density: 512 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 31:
Table 7:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
CKE
H
H
L
L
n - 1
Truth Table 2 – CKE
Notes 1–4 apply to entire table; notes appear below
CKE
WRITE with Auto Precharge Interrupted by a WRITE
H
H
L
L
Internal
States
n
Notes:
Note:
COMMAND
ADDRESS
BANK m
Reading or writing
BANK n
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
Current State
Clock suspend
Clock suspend
All banks idle
All Banks idle
CLK
Power-down
Power-down
DQ
clock edge.
MAND
clock edge n + 1 (provided that
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the
period.
the next command at clock edge n + 1.
Self refresh
Self refresh
DQM is LOW.
n
is the logic state of CKE at clock edge n; CKE
Page Active
T0
NOP
n
.
t
n
XSR period. A minimum of two NOP commands must be provided during
WRITE - AP
is the command registered at clock edge n, and ACTION
BANK n,
Page Active
BANK n
COL a
T1
D
a
IN
WRITE with Burst of 4
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
a + 1
T2
D
NOP
See Table 8 on page 38
IN
AUTO REFRESH
WRITE or NOP
37
COMMAND
a + 2
T3
D
t
NOP
IN
CKS is met).
X
X
X
X
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK m,
WRITE - AP
COL d
BANK m
T4
D
n
t
d
IN
Interrupt Burst, Write-Back
WR - BANK n
WRITE with Burst of 4
Transitioning Data
T5
d + 1
NOP
D
n - 1
IN
Maintain clock suspend
512Mb: x4, x8, x16 SDRAM
Maintain power-down
was the state of CKE at the previous
Maintain self refresh
Clock suspend entry
Power-down entry
Exit clock suspend
T6
Self refresh entry
Exit power-down
d + 2
NOP
Exit self refresh
D
t RP - BANK n
Precharge
IN
ACTION
©2000 Micron Technology, Inc. All rights reserved.
Don’t Care
T7
d + 3
NOP
D
t WR - BANK m
IN
Write-Back
n
n
is a result of COM-
Operations
Notes
t
7
XSR is
5
6
t
XSR