MT48LC64M8A2TG-75 IT:C Micron Technology Inc, MT48LC64M8A2TG-75 IT:C Datasheet - Page 51

DRAM Chip SDRAM 512M-Bit 64Mx8 3.3V 54-Pin TSOP-II Tray

MT48LC64M8A2TG-75 IT:C

Manufacturer Part Number
MT48LC64M8A2TG-75 IT:C
Description
DRAM Chip SDRAM 512M-Bit 64Mx8 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC64M8A2TG-75 IT:C

Package
54TSOP-II
Density
512 Mb
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
6|5.4 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 35:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMU
COMMAND
BA0, BA1
A11, A12
A0–A9,
DQM/
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
COLUMN m
Clock Suspend Mode
READ
T0
BANK
t CMH
t CKH
t AH
t AH
t AH
Notes:
2
t CMS
t CK
T1
NOP
t CMH
1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
t CL
t CKS t CKH
T2
NOP
t LZ
t CH
t AC
T3
D
OUT
m
T4
NOP
51
t OH
t AC
D
OUT
T5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
m + 1
t HZ
T6
NOP
512Mb: x4, x8, x16 SDRAM
COLUMN e 2
t DS
BANK
WRITE
D
T7
in
e
t DH
©2000 Micron Technology, Inc. All rights reserved.
Timing Diagrams
T8
D
T9
NOP
in
Don’t Care
Undefined
+ 1

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