XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 132
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XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Chapter 4: Block RAM
132
RAMB18 and RAMB36 Port Mapping Design Rules
Cascadable Block RAM
Byte-wide Write Enable
•
The Virtex-5 FPGA block RAM are configurable to various port widths and sizes.
Depending on the configuration, some data pins and address pins are not used.
page 126
Table
1.
2.
3.
4.
5.
To use the cascadable block RAM feature:
1.
2.
3.
4.
5.
6.
Figure 4-7
The following rules should be considered when using the byte-wide write enable feature:
•
•
•
When using these attributes, if both write ports or both read ports are set to 0, the
Xilinx ISE tools will not implement the design. In simple dual-port mode, the port
width is fixed and the read port width is equal to the write port width. The RAMB18
has a data port width of 36, while the RAMB36 has a data port width of 72.
When using RAMB36, if the DI[A|B] pins are less than 32 bits wide, concatenate
(32 – DI_BIT_WIDTH) logic zeros to the front of DI[A|B].
If the DIP[A|B] pins are less than 4-bits wide, concatenate (4 – DIP_BIT_WIDTH) logic
zeros to the front of DIP[A|B]. DIP[A|B] can be left unconnected when not in use.
DO[A|B] pins must be 32 bits wide. However, valid data is only found on pins
DO_BIT_WIDTH – 1 down to 0.
DOP[A|B] pins must be 4 bits wide. However, valid data is only found on pins
DOP_BIT_WIDTH – 1 down to 0. DOP[A|B] can be left unconnected when not in use.
ADDR[A|B] pins must be 16 bits wide. However, valid addresses for non-cascadable
block RAM are only found on pin 14 to (15 – address width). The remaining pins,
including pin 15, should be tied High. Address width is defined in
Two RAMB36 primitives must be instantiated.
Set the RAM_EXTENSION_A and RAM_EXTENSION_B attribute for one RAMB36 to
UPPER, and another to LOWER.
Connect the upper RAMB36’s CASCADEINA and CASCADEINB ports to the
CASCADEOUTA and CASCADEOUTB ports of the lower RAMB36. The
CASCADEOUT ports for the upper RAMB36 do not require a connection. Connect the
CASCADEIN ports for the lower RAMB36 to either logic High or Low.
The data output ports of the lower RAMB36 are not used. These pins are unconnected.
If placing location constraints on the two RAMB36s, they must be adjacent. If no
location constraint is specified, the Xilinx ISE software will automatically manage the
RAMB36 locations.
The address pins ADDR[A|B] must be 16 bits wide. Both read and write ports must be
one bit wide.
In x36 mode, WE[3:0] is connected to the four user WE inputs.
In x18 mode, WE[0] and WE[2] are connected and driven by the user WE[0], while
WE[1], and WE[3] are driven by the user WE[1].
In x9, x4, x2, x1, WE[3:0] are all connected to a single user WE.
4-6, the following rules are useful to determine port connections for the RAMB36:
shows the pins used in various configurations. In addition to the information in
shows the cascadable block RAM.
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table 4-6, page
Table 4-6,
126.
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