XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 65
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
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XC5VSX95T-2FF1136I
Manufacturer:
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Quantity:
20 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Output Clocks
DCM During Configuration and Startup
Deskew Adjust
Any or all of the DCM’s nine clock outputs can be used to drive a global clock network.
The fully-buffered global clock distribution network minimizes clock skew caused by
loading differences. By monitoring a sample of the output clock (CLK0), the deskew circuit
compensates for the delay on the routing network, effectively eliminating the delay from
the external input port to the individual clock loads within the device.
Output pin connectivity carries some restrictions. The DCM clock outputs must drive a
global clock buffer BUFGCTRL. The DCM clock outputs can not drive general routing. To
use dedicated routing, the DCM clock outputs must drive BUFGCTRLs on the same top or
bottom half of the device. If the DCM and BUFGCTRL are not on the same top or bottom
half, local routing is used and the DCM might not deskew properly.
Do not use the DCM output clock signals until after activation of the LOCKED signal. Prior
to the activation of the LOCKED signal, the DCM output clocks are not valid.
During the FPGA configuration, the DCM is in reset and starts to lock at the beginning of
the startup sequence. A DCM requires both CLKIN and CLKFB input clocks to be present
and stable when the DCM begins to lock. If the device enters the configuration startup
sequence without an input clock, or with an unstable input clock, then the DCM must be
reset after configuration with a stable clock.
The following startup cycle dependencies are of note:
1.
2.
3.
The DESKEW_ADJUST attribute sets the value for a configurable, variable-tap delay
element to control the amount of delay added to the DCM feedback path (see
The default value is -g LCK_cycle:NoWait. When this setting is used, the startup
sequence does not wait for the DCM to lock. When the LCK_cycle is set to other values,
the configuration startup remains in the specified startup cycle until the DCM is
locked.
Before setting the LCK_cycle option to a startup cycle in BitGen, the DCM’s
STARTUP_WAIT attribute must be set to TRUE.
If the startup sequence is altered (by using the BitGen option), do not place the
LCK_cycle (wait for the DCM to lock) before the GTS_cycle (deassert GTS). Incorrect
implementation results in the DCM not locking and an incomplete configuration.
www.xilinx.com
DCM Design Guidelines
Figure
2-4).
65
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