XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 360
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
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Chapter 8: Advanced SelectIO Logic Resources
360
ISERDES_NODELAY Clocking Methods
NUM_CE Attribute
SERDES_MODE Attribute
Networking Interface Type
X-Ref Target - Figure 8-5
The NUM_CE attribute defines the number of clock enables (CE1 and CE2) used. The
possible values are 1 and 2 (default = 2).
The SERDES_MODE attribute defines whether the ISERDES_NODELAY module is a
master or slave when using width expansion. The possible values are MASTER and
SLAVE. The default value is MASTER. See
The phase relationship of CLK and CLKDIV is important in the serial-to-parallel
conversion process. CLK and CLKDIV are (ideally) phase-aligned within a tolerance.
There are several clocking arrangements within the FPGA to help the design meet the
phase relationship requirements of CLK and CLKDIV. The only valid clocking
arrangements for the ISERDES_NODELAY block using the networking interface type are:
•
•
•
Figure 8-5: Internal Connections of ISERDES_NODELAY When in Memory Mode
CLK driven by BUFIO, CLKDIV driven by BUFR
CLK driven by DCM, CLKDIV driven by the CLKDV output of the same DCM
CLK driven by PLL, CLKDIV driven by CLKOUT[0:5] of same PLL
CLKDIV
OCLK
CLK
D
ICE
ICE
FF0
FF1
www.xilinx.com
ICE
ICE
ISERDES Width
FF2
FF3
FF4
FF5
Expansion.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
FF6
FF7
FF8
FF9
ug190_8_05_100307
Q1
Q2
Q3
Q4
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