XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 377
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
OSERDES Latencies
OSERDES Timing Model and Parameters
The input to output latencies of OSERDES blocks depend on the DATA_RATE and
DATA_WIDTH attributes. Latency is defined as a period of time between the following
two events: (a) when the rising edge of CLKDIV clocks the data at inputs D1–D6 into the
OSERDES, and (b) when the first bit of the serial stream appears at OQ.
summarizes the various OSERDES latency values.
Table 8-10: OSERDES Latencies
This section discusses all timing models associated with the OSERDES primitive.
Table 8-11
characteristics in the Virtex-5 FPGA Data Sheet.
Table 8-11: OSERDES Switching Characteristics
Setup/Hold
T
T
T
T
T
Sequential Delays
T
T
OSDCK_D
OSDCK_T
OSDCK_T
OSCCK_OCE
OSCCK_TCE
OSCKO_OQ
OSCKO_TQ
DATA_RATE
DDR
SDR
/T
/T
describes the function and control signals of the OSERDES switching
Symbol
/T
/T
/T
OSCKD_T
OSCKD_T
OSCKD_D
OSCKC_TCE
OSCKC_OCE
www.xilinx.com
D input Setup/Hold with respect to CLKDIV
T input Setup/Hold with respect to CLK
T input Setup/Hold with respect to CLKDIV
OCE input Setup/Hold with respect to CLK
TCE input Setup/Hold with respect to CLK
Clock to Out from CLK to OQ
Clock to Out from CLK to TQ
DATA_WIDTH
Output Parallel-to-Serial Logic Resources (OSERDES)
10:1
2:1
3:1
4:1
5:1
6:1
7:1
8:1
4:1
6:1
8:1
Description
1 CLK cycle
3 CLK cycles
4 CLK cycles
4 CLK cycles
5 CLK cycles
5 CLK cycles
6 CLK cycles
1 CLK cycle
3 CLK cycles
4 CLK cycles
4 CLK cycles
Latency
Table 8-10
377
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