XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 169
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XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
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Table 4-25: Block RAM ECC Mode Timing Parameters
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Setup and Hold Relative to Clock (CLK)
Clock to Out Delays
(Standard ECC Mode)
(Standard ECC Mode)
(Encode-only Mode)
(Encode-only Mode)
(register mode)
T
T
T
T
(latch mode)
RDCK_DI_ECC
RCKD_DI_ECC
RDCK_DI_ECC
RCKD_DI_ECC
Parameter
T
T
RCKO_DO
RCKO_DO
Block RAM ECC Mode Timing Parameters
T
Encode-Only ECC Write Timing
Encode-Only ECC Read Timing
Decode-Only ECC Write Timing
Decode-Only ECC Read Timing
RxCK_x
•
•
•
•
•
•
Table 4-25
= Setup time (before clock edge) and T
Clock to Output
Clock to Output
Setup/hold time for WREN and WRADDR are the same as standard ECC.
At time TRDCK_DI_ECC (encode-only ECC), before time T1W, write data A (hex)
becomes valid at the DI[63:0] inputs of the block RAM.
At time TRCKO_ECC_PARITY (encode-only ECC), after time T1W, ECC parity data
PA (hex) becomes valid at the ECCPARITY[7:0] output pins of the block RAM.
Encode-only ECC read timing are the same as normal block RAM read timing.
Decode-only ECC write timing is the same as normal block RAM write timing.
Decode-only ECC read timing is the same as standard ECC read timing.
Data inputs
Data inputs
Function
shows the Virtex-5 FPGA block RAM ECC mode timing parameters.
(1)
(1)
(2)
(2)
CLK to DO
CLK to DO
Control
Signal
www.xilinx.com
DI
DI
(Figure
Time before the clock that data must be stable at the DI
inputs of the block RAM. Standard ECC mode.
Time after the clock that data must be stable at the DI
inputs of the block RAM. Standard ECC mode.
Time before the clock that data must be stable at the DI
inputs of the block RAM. Encode-only mode.
Time after the clock that data must be stable at the DI
inputs of the block RAM. Encode-only mode.
Time after the clock that the output data is stable at the
DO outputs of the block RAM (without output
register).
Time after the clock that the output data is stable at the
DO outputs of the block RAM (with output register).
RCKx_x
= Hold time (after clock edge)
4-31)
Description
Built-in Error Correction
169
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