XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 75
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
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- Download datasheet (14Mb)
Application Examples
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Standard Usage
Board-Level Clock Generation
The Virtex-5 FPGA DCM can be used in a variety of creative and useful applications. The
following examples show some of the more common applications.
The circuit in
access to RST and LOCKED pins. This example shows the simplest use case for a DCM.
X-Ref Target - Figure 2-8
The board-level clock generation example in
generate output clocks for other components on the board. This clock can then be used to
interface with other devices. In this example, a DDR register is used with its inputs
connected to GND and V
stays within global routing until it reaches the output register. The quality of the clock is
maintained.
The board-level clock generation example in
the clock generation for a forwarded clock on the board.
Figure 2-8
IBUFG
IBUF
shows DCM_BASE implemented with internal feedback and
CC
www.xilinx.com
. Because the output of the DCM is routed to BUFG, the clock
Figure 2-8: Standard Usage
CLKIN
CLKFB
RST
DCM_BASE
Figure
Figure 2-9
2-10, with internal feedback, illustrates
CLKFX180
CLK2X180
LOCKED
CLK180
CLK270
CLKDV
CLKFX
illustrates how to use a DCM to
CLK2X
CLK90
CLK0
Application Examples
ug190_2_08_032506
BUFG
OBUF
75
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