ISPGDX160VA-3B208 LATTICE SEMICONDUCTOR, ISPGDX160VA-3B208 Datasheet - Page 20

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ISPGDX160VA-3B208

Manufacturer Part Number
ISPGDX160VA-3B208
Description
Digital Crosspoint 208-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet

Specifications of ISPGDX160VA-3B208

Package
208FBGA
Number Of Arrays
1
Power Supply Type
Dual
Maximum Dual Supply Voltage
3.6 V
Minimum Dual Supply Voltage
2.3|3 V
Output Level
TTL

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ispGDX160V timings are specified with a GRP load
(fanout) of four I/O cells. The figure below shows the ∆
GRP Delay with increased GRP loads. These deltas
External Timing Parameters (Continued)
ispGDX160V Maximum
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0 4 10
20
I/O Cell Fanout
GRP Delay vs. I/O Cell Fanout
19
30
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
which do not use the GRP have no fanout delay adder.
Specifications ispGDX160V
40
50
60
70

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