ISPGDX160VA-3B208 LATTICE SEMICONDUCTOR, ISPGDX160VA-3B208 Datasheet - Page 8

• Manufacturer Part Number: ISPGDX160VA-3B208
• Description: Digital Crosspoint 208-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPGDX160VA-3B208

• Package: 208FBGA
• Number Of Arrays: 1
• Power Supply Type: Dual
• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 2.3|3 V
• Output Level: TTL

Figure 5. Address Demultiplex/Data Buffering
Figure 6. Data Bus Byte Swapper
Figure 7. Four-Port Memory Interface
Applications (Continued)
Note: All OE and SEL lines driven by external arbiter logic (not shown).
D8-15
D0-7
I/OA
OEA OEB
I/OA I/OB
OEA OEB
XCVR
XCVR
I/OB
I/OA
OEA
D
CLK
Address
XCVR
Latch
Port #1
OE1
Port #2
OE2
Port #3
OE3
Port #4
OE4
Bidirectional
16-Bit MUX
OEB
I/OB
4-to-1
Q
I/OA I/OB
OEA OEB
I/OA I/OB
OEA OEB
Memory
D8-15
D0-7
XCVR
XCVR
SEL0
SEL1
OEM
Port
Buffered
Data
Address
To Memory/
Peripherals
To
Memory
Specifications ispGDX160V/VA
7
Designing with the ispGDXV/VA
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O0-39 (160 I/O device), it is not
possible to use I/O0 and I/O9 in the same MUX function.
As previously discussed, data path functions will be
assigned early in the design process and these restric-
tions are reasonable in order to optimize speed and cost.
User Electronic Signature
The ispGDXV/VA Family includes dedicated User Elec-
tronic Signature (UES) E
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific com-
mand. This information can be read even when the
security cell is programmed.
Security
The ispGDXV/VA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
2
CMOS storage to allow users