MT46V32M16P-5B:F Micron Technology Inc, MT46V32M16P-5B:F Datasheet - Page 71

• Manufacturer Part Number: MT46V32M16P-5B:F
• Description: DRAM Chip DDR SDRAM 512M-Bit 32Mx16 2.6V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V32M16P-5B:F

• Density: 512 Mb
• Maximum Clock Rate: 400 MHz
• Package: 66TSOP
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Package / Case: 66-TSOP
• Organization: 32Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 215mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 36:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
DQ8–DQ15 and UDQS collectively
DQ0–DQ7 and LDQS collectively
DQ (first data no longer valid)
DQ (first data no longer valid)
DQ (first data no longer valid)
DQ (first data no longer valid)
x16 Data Output Timing –
Notes:
DQ (last data valid)
DQ (last data valid)
DQ (last data valid)
DQ (last data valid)
UDQS
LDQS 3
1.
2.
3. DQ transitioning after DQS transition define the
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5.
6. The data valid window is derived for each DQS transition and is
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
CK#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK
4
4
4
4
4
4
4
4
4
4
6
3
7
7
7
7
7
7
7
7
7
7
6
t
t
transition, and ends with the last valid DQ transition.
byte, and UDQS defines the upper byte.
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
T1
t HP 1
t
DQSQ,
t HP 1
t
CL or
t
t DQSQ 2
HP:
t QH 5
t DQSQ 2
T2
t QH 5
t
t
t
QH =
Data valid
QH, and Data Valid Window
CH clock transition collectively when a bank is active.
window
T2
T2
T2
Data valid
t HP 1
window
71
T2
T2
T2
t
HP -
T2n
t DQSQ 2
t QH 5
t DQSQ 2
t QH 5
Data valid
t
window
QHS.
t HP 1
T2n
T2n
T2n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Data valid
window
T2n
T2n
T2n
T3
t DQSQ 2
t QH 5
t DQSQ 2
512Mb: x4, x8, x16 DDR SDRAM
t QH 5
t HP 1
t
Data valid
DQSQ window. LDQS defines the lower
window
Data valid
T3
T3
T3
window
T3
T3n
T3
T3
t DQSQ 2
t DQSQ 2
t HP 1
t QH 5
t QH 5
Data valid
window
Data valid
T4
T3n
window
T3n
T3n
©2000 Micron Technology, Inc. All rights reserved.
T3n
T3n
T3n
t
QH -
t
DQSQ.
Operations