TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet
TSEV81102G0TPZR3
Specifications of TSEV81102G0TPZR3
TSEV81102G0TPZR3 Summary of contents
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Features • Programmable DMUX Ratio: – 1:4: Data Rate Max = 750 Msps – PD (8b/10b) < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 1.5 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – ...
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Block Diagram Figure 1. Block Diagram Data Path FS/8 BIST 8/10 mux 8/10 even odd master master latch latch odd even slave slave latch latch 8/10 Even Ports TS81102G0 2 delay NAP B 2 mux Phase control ClkPar (8 ...
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Internal Timing Diagram This diagram corresponds to an established operation of the DMUX with Synchronous Reset. Figure 2-1. Internal Timing Diagram 500 ps min Data In N N Fs/2 = ClkPar ...
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Functional Description The TS81102G0 is a demultiplexer based on an advanced high-speed bipolar technology featur- ing a cutoff frequency of 25 GHz. Its role is to reduce the data rate so that the data can be processed at the ...
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Main Function Description 4.1 Programmable DMUX Ratio The conversion ratio is programmable: 1:4 or 1:8. Figure 4-1. 4.2 Parallel Output Mode Figure 4-2. 2105D–BDC–07/05 Programmable DMUX Ratio Input Words: 1,2,3,4,5,6,7,8,... 1:4 Input Words: 1,2,3,4,5,6,7,8,... 1:8 Parallel Mode ClkIn DR ...
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Input Clock Sampling Delay Adjust (DEMUXDELADJCTRL) The input clock phase can be adjusted with an adjustable delay (from 250 to 750 ps). This is to ensure a proper phase between the clock and input data of the DMUX. 4.4 ...
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The front edge of this clock is synchronized with Clkln inside the DMUX, and generates a 200 ps reset pulse. This reset pulse occurs during a fixed level of Clkln. If the DMUX was synchronized with Syncreset previous to a ...
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Differential Output Data The output clock for the ADC is generated through a 50Ω loaded long tailed. The 50Ω resistor is connected to the ground pad via a diode. The levels are (on the 100Ω differential termination resistor): ...
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Following are three application examples for these buffers: ECL/PECL/TTL. Please note that it is possible to have any other odd output format as far as current (36 mA max) and voltage (Vplus Dout – V depends on the load to ...
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Specifications 5.1 Absolute Maximum Ratings Table 5-1. Absolute Maximum Ratings Parameter Positive supply voltage Positive output buffer supply voltage Negative supply voltage Analog input voltages ECL 50Ω input voltage Maximum difference between ECL 50Ω input voltages Data output current ...
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Recommended Operating Conditions Table 5-2. Recommended Operating Conditions Parameter Positive supply voltage Positive output buffer supply voltage Positive output buffer supply voltage Positive output buffer supply voltage Negative supply voltage Operating temperature range 5.3 Electrical Operating Characteristics Tj (typical) ...
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Table 5-3. Electrical Specifications (Continued) Parameter Supply Currents ECL (50Ω) and PECL (50Ω) V (for every configuration) CC • 1:8, 8 bits • 1:8, 10 bits • 1:4, 8 bits • 1:4, 10 bits TTL (75Ω) V (for every configuration) ...
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Table 5-3. Electrical Specifications (Continued) Parameter TTL (75Ω) • 1:8, 8 bits • 1:8, 10 bits • 1:4, 8 bits • 1:4, 10 bits Delay Adjust Control DMUXDelAdjCtrl differential voltage • 250 ps • 500 ps • 750 ps • ...
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Table 5-3. Electrical Specifications (Continued) Parameter Digital Inputs DATA Input Voltages (ECL) • Logic “0” voltage • Logic “1” voltage CTRL Input Voltages (TTL) • Logic “0” voltage • Logic “1” voltage Note: 1. The supply current I PLUSD - ...
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Table 5-4. Switching Performances (Continued) Parameter Synchronous Reset Setup time from SyncReset to Clkln DR input clock DR/2 input clock Hold time from Clkln to SyncReset DR input clock DR/2 input clock Rise/fall for (10% – 90%) Input Data Setup ...
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Table 5-4. Switching Performances (Continued) Parameter Rise/fall time for (10% – 90%) ADC Delay Adjust Input frequency Input pulse width (high) Input pulse width (low) Input rise/fall time Output rise/fall time Data output delay (typical delay adjust setting) Output delay ...
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Explanation of Test Levels Table 5-5. Num Notes: 5.5.1 Input Clock Timings Figure 5-1. Input Clock TC2 TFCKIN TC1 TRCKIN Clkln TSCKIN Data [0..9] d1 Clkln Type = 1 DataReady Mode (DR) 2105D–BDC–07/05 Explanation ...
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ADC Delay Adjust Timing Diagram Figure 5-2. ADC Delay Adjust Timing Diagram TC2ADA TFIADA TC1ADA TRIADA ADCDelAdjIn TFOADA ADCDelAdjOut 5.5.3 Timing Diagrams with Asynchronous Reset With a nominal tuning of DMUXDelAdj at a frequency of 1.5 GHz, d1 and ...
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Figure 5-4. Start with Asynchronous Rest, 1:8 Ratio, DR/2 Mode ASyncReset Clkn Internal Port Selection (not available out of the DEMUX) I[0..9] A[0..9] B[0..9] C[0..9] D[0..9] E[0..9] F[0..9] G[0..9] H[0..9] DR With a nominal tuning of DMUXDelAdj, at 750 MHz ...
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Figure 5-6. Start with Asynchronous Reset, 1:4 Ratio, DR/2 Mode ASyncReset Clkn Internal Port Selection (not available out of the DEMUX) I[0..9] A[0..9] B[0..9] C[0..9] D[0..9] DR 5.5.4 Timing Diagrams with Synchronous Reset Examples of Synchronous Reset usefulness in case ...
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Figure 5-7. Synchronous Reset, 1:8 Ratio, DR Mode SyncReset Clkn I[0.. Internal Port Selection A B (not available out of the DEMUX) A[0..9] B[0..9] C[0..9] D[0..9] E[0..9] F[0..9] G[0..9] H[0..9] DR 5.5.4.2 Synchronous Reset, 1:4 Ratio, DR Mode ...
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Figure 5-8. (not available out of the DEMUX) 5.5.4.3 Synchronous Reset, 1:8 Ratio, DR/2 Mode The desynchronization event happens after the selection of Port C. DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln internal propagation delay TCPD. After ...
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Synchronous Reset, 1:4 Ratio, DR/2 Mode The desynchronization event happens after the selection of Port C. DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln internal propagation delay TCPD. Figure 5-10. Synchronous Reset, 1:4 ratio, DR/2 Mode SyncReset ...
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Package Description 6.1 Pin Description Table 6-1. Enter Title of Manual Pin Description Type Name I[0…9] Digital Inputs Clkln A[0…9] → H[0…9] Outputs DR RefA → RefH ClklnType RatioSel Bist Control Signals SwiAdj Diode NbBit AsyncReset SyncReset DMUXDelAdjCtrl Synchronization ...
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TBGA 240 Package – Pinout Row Col Name ...
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Figure 6-1. TBGA 240 Package: Bottom View RstSyncb Demuxdeladjctrcl A8 A6 RstSync Asyncreset Demuxdeladjctrclb GND GND GND DIODE VPLUSD I0 GND VCC VCC I0b I1b I1 VEE VEE I2 I2b GND GND I3 ...
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Outline Dimensions Figure 6-2. Package Dimension – 240 Tape Ball Grid Array 0. Corner 45 degree 0.5 mm chamfer (4 PLCS) Top View Detail A Side View P Detail A 5 2105D–BDC–07/ ...
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Thermal and Moisture Characteristics 6.4.1 Thermal Resistance from Junction to Case: RTHJC The Rth from junction to case for the TBGA package is estimated at 1.05°C/W that can be bro- ken down as follows: • Silicon: 0.1°C/W • Die ...
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Figure 6-3. Thermal Resistance from Junction to Bottom of Balls DEMUX − Axpproximative Model for 240 TBGA Assumptions: Square die 7 mm², 75 µm thick Epoxy/Ag glue, 0.40 mm copper thickness under die, Sn60Pb40 columns diameter ...
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Moisture Characteristic This device is sensitive to moisture (MSL3 according to the JEDEC standard). The shelf life in a sealed bag is 12 months at < 40°C and < 90% relative humidity (RH). After this bag is opened, devices ...
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Applying the Enter Title of Manual DMUX The TSEV81102G0 DMUX evaluation board is designed to be connected with the TSEV8388G and TSEV83102G0 ADC evaluation boards. Figure 7-1. Analog Input 10bits 2 GHz TS83102G0 Please refer to the "ADC and ...
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ADC to DMUX Connections The DMUX inputs configuration has been optimized to be connected to the TS8388B ADC. The die in the TBGA package is up. For the ADC, different types of packages can be used such as CBGA ...
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... Ordering Information Table 9-1. Ordering Information Part Number Package TS81102G0VTP TBGA 240 TSEV81102G0TPZR3 TBGA 240 10. Datasheet Status Description Table 10-1. Datasheet Status Objective specification Target specification Preliminary specification α-site Preliminary specification β-site Product specification Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device ...
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Addendum This section has been added to the description of the device for better understanding of the syn- chronous reset operation. It puts particular stress on the setup and hold times defined in the switching characteristics table full-speed (1.5 ...
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Figure 10-2. Synchronous Reset Operation in DR Mode, 1:4 ratio, 750 MHz (Full-speed) – TIMINGS Fs Time Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If ...
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Operation in DR/2 Mode In DR/2 mode, the DMUX input clock can run 750 MHz in 1:8 ratio or 375 MHz in 1:4 ratio, since the DR/2 clock from the ADC is half the sampling frequency. ...
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Figure 10-8. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 750 MHz (Full-speed) – Timings Fs/2 Times Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...