TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 21

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

Figure 5-7.
5.5.4.2
2105D–BDC–07/05
(not available out of the DEMUX)
Internal Port Selection
Synchronous Reset, 1:4 Ratio, DR Mode
Synchronous Reset, 1:8 Ratio, DR Mode
SyncReset
G[0..9]
C[0..9]
D[0..9]
H[0..9]
A[0..9]
B[0..9]
E[0..9]
F[0..9]
I[0..9]
Clkn
DR
The desynchronization event happens after the selection of Port C.
DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln internal propagation delay TCPD.
After selection of port C, instead of selecting port D, the de-synchronization makes the port
selection to restart on port A. Since port D was not selected, the data are not output to the ports
but the last data (d1 to d4) are latched till next selection of port D. d5 to d8 are lost.
The synchronous reset ensures a re-synchronization of the port selection.
d0
A
d1
B
TDRR
d2
C
d3
D
d4
E
d5
F
TDRF
d6
TOD
G
TSSR
TCPD
d7
H
THSR
d8
A
De-synchronization
d9 d10 d11
B
C
Period of uncertainty due to desynchronization
A
d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27
B
C
TSRDR
Re-synchronization
D
TSSR
d1
d2
d3
d4
d5
d6
d7
d8
E
THSR
A
B
TDRR
C
D
E
F
TDRF
TOD
G
TSSR
TCPD
TS81102G0
H
THSR
A
B
d17
d18
d19
d20
d21
d22
d23
d24
C
D
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