TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 8

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

4.10
4.11
8
50Ω Differential Output Data
Single-ended Output Data
TS81102G0
The output clock for the ADC is generated through a 50Ω loaded long tailed. The 50Ω resistor is
connected to the ground pad via a diode. The levels are (on the 100Ω differential termination
resistor): Vol = -1.4V, Voh = -1.0V.
Figure 4-6.
To reduce the pin number and power consumption of the DMUX, the eight output ports are
To reach the high frequency output (up to 93.75 MHz, i.e. 187.5 Msps rate) with a reasonable
power consumption, the swing must be limited to a maximum of ±500 mV. The common mode is
adjustable from -1.3V to +2V, with V
ence level (common mode) is available (one level by output port).
The output buffers are of ECL type (open emitters – not resistive adapted impedances). They
are designed for a 15 mA average output current, and may be used with a 50Ω termination
impedance.
Figure 4-7.
single-ended.
50Ω Differential Output Data
Single-ended Output Data
ADCDelAdjOut
PLUSD
V EE
Dout pins. To ensure better noise immunity, a refer-
V PLUSD
Gnd
ADCDelAdjOutb
PadOut
2105D–BDC–07/05