TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 19

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

Figure 5-4.
Figure 5-5.
2105D–BDC–07/05
(not available out of the DEMUX)
(not available out of the DEMUX)
Start with Asynchronous Rest, 1:8 Ratio, DR/2 Mode
Start with Asynchronous Reset, 1:4 Ratio, DR Mode
Internal Port Selection
Internal Port Selection
ASyncReset
ASyncReset
C[0..9]
D[0..9]
G[0..9]
H[0..9]
A[0..9]
B[0..9]
E[0..9]
F[0..9]
I[0..9]
Clkn
With a nominal tuning of DMUXDelAdj, at 750 MHz (1:4 mode) d1 data is lost because of the
internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins and is
used to obtain good setup and hold times between Clkln and the input data.
With a nominal tuning of DMUXDelAdj, at 750 MHz (1:4 mode) d1 data is lost because of the
internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins and is
used to obtain good setup and hold times between Clkln and the input data. This timing diagram
does not change with the opposite phase of Clkln.
DR
A[0..9]
B[0..9]
C[0..9]
D[0..9]
I[0..9]
Clkn
DR
TARDR
PWAR
TARDR
PWAR
d1
A
A
d1
TDRR
TCPD
TCPD
d2
TRDR
d2
d3
B
B
TDRR
d4
C
d3
d5
D
TDRF
C
TOD
d6
E
TFDR
d7
d4
F
TOD
TDRF
d8
D
G
TCPD
d9
H
d5
d10
TDRR
A
TPD
A
d11
B
d2
d3
d4
TPD
d6
d12
C
TRDR
B
d13
d3
d4
d5
d6
d7
d8
d9
D
d7
d14
E
TROD/TFOD
TS81102G0
d15
C
TOD
F
TROD/TFOD
TOD
d16
G
d8
TFDR
d5
d6
d7
d8
d17
D
d10
d11
d12
d13
d14
d15
d16
d17
H
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