TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 20

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

Figure 5-6.
5.5.4
5.5.4.1
20
TS81102G0
Timing Diagrams with Synchronous Reset
(not available out of the DEMUX)
Synchronous Reset, 1:8 Ratio, DR Mode
Start with Asynchronous Reset, 1:4 Ratio, DR/2 Mode
Internal Port Selection
ASyncReset
Examples of Synchronous Reset usefulness in case of desynchronization of DMUX output port
selection.
The desynchronization event happens after the selection of Port C.
DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln internal propagation delay TCPD.
After selection of port C, instead of selecting port D, the de-synchronization makes the port
selection to restart on port A. Since port H was not selected, the data are not output to the ports
but the last data (d1 to d8) are latched till next selection of port H. d9 to d16 are lost.
The synchronous reset ensures a re-synchronization of the port selection.
C[0..9]
D[0..9]
A[0..9]
B[0..9]
I[0..9]
Clkn
DR
TARDR
PWAR
d1
A
TDRR
TCPD
TRDR
d2
B
d3
TOD
TDRF
C
TFDR
d4
TCPD
D
d5
A
TPD
d2
d3
d4
d6
B
d7
TOD
C
TROD/TFOD
d5
d6
d7
d8
2105D–BDC–07/05
d8