TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 23

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

5.5.4.4
Figure 5-10. Synchronous Reset, 1:4 ratio, DR/2 Mode
2105D–BDC–07/05
(not available out of the DEMUX)
Internal Port Selection
Synchronous Reset, 1:4 Ratio, DR/2 Mode
SyncReset
A[0..9]
B[0..9]
C[0..9]
D[0..9]
I[0..9]
Clkn
DR
The desynchronization event happens after the selection of Port C.
DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln internal propagation delay TCPD.
After selection of port C, instead of selecting port D, the de-synchronization makes the port
selection to restart on port A. Since port D was not selected, the data are not output to the ports
but the last data (d1 to d4) are latched till next selection of port D. d5 to d8 are lost.
The synchronous reset ensures a re-synchronization of the port selection.
Note:
d1
In case of low clock frequency and start with asynchronous reset, only the first data is lost and the
first data to be processed is the second one. This data goes out of the DEMUX by the port B.
B
d2
C
d3
D
d4
Period of uncertainty due to desynchronization
A
d5
B
d6
C
d7
TSSR
d1
d2
d3
d4
TCPD
A
d8
THSR
A
d9
B
d10
TDRF
TOD
C
d11
D
d12
TDRR
A
d13
d11
d12
d10
d9
TS81102G0
B
d14
C
d15
D
d16
23