FIN1022M_NL Fairchild Semiconductor, FIN1022M_NL Datasheet - Page 5

• Manufacturer Part Number: FIN1022M_NL
• Manufacturer: Fairchild Semiconductor

Specifications of FIN1022M_NL

• Array Configuration: 2x2
• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC N
• Pin Count: 16
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Cascading Capability: No
• On-chip Buffers: No
• On-chip Decoder: No
• On-chip Latch Circuit: No
• On-chip Mux/demux: Yes
• Programmable: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / RoHS Status: Compliant

Required Specifications
1. When the true and complement LVDS outputs (having
2. When the true and complement LVDS outputs (having
a 75
3.75 k
k
sweeps from 0 to 2.4V, the DC V
maintained (see Figure 1).
a 5 pF capacitor attached between outputs) are con-
nected with 37.5
then the common point does not vary by more than 150
mV under all process, temperature and voltage condi-
tions when the outputs switch either from LOW-to-
HIGH or from HIGH-to-LOW (see Figure 2).
resistors are connected to a voltage source that
connected between outputs) are connected to
resistors and the common point of those 3.75
resistors each to common point,
FIGURE 2. Dynamic V
FIGURE 1. Common Mode Supply Test Circuit
OD
and V
OD
are still
OS
Test Circuit and Waveforms
5
3. Pull-down resistors are required on Enable (EN
4. Fail safe protection on the outputs that draw less than
5. In the disabled state the outputs can go beyond V
EN
20 A of current (worst case) on the LVDS inputs. In
this condition, if the input is in fail safe selected to
OUT
OUT
from being amplified when the connection is broken.
but there should be no appreciable leakage (see I
and I
1
) and select (SEL
0
0
OFF
/OUT
HIGH and OUT
specifications)
0
(say) and the outputs are Enabled then
0
and SEL
0
LOW. This prevents noise
1
) inputs.
www.fairchildsemi.com
0
and
OZD
CC