82P2281PFG8 IDT, Integrated Device Technology Inc, 82P2281PFG8 Datasheet - Page 12

• Manufacturer Part Number: 82P2281PFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

FEATURES
LINE INTERFACE
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FRAMER
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IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
 2009 Integrated Device Technology, Inc.
The device can be configured as T1, E1 or J1
Supports T1/E1/J1 long haul/short haul line interface
HPS for 1+1 protection without external relays
Receive sensitivity exceeds -36 dB @ 772 Hz and -43 dB @ 1024
Hz
Selectable internal line termination impedance: 100 Ω (for T1), 75
Ω / 120 Ω (for E1) and 110 Ω (for J1)
Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) line encod-
ing/decoding
Provides T1/E1/J1 short haul pulse templates, long haul LBO (per
ANSI T1.403 and FCC68: 0 dB, -7.5 dB, -15 dB, -22 dB) and user-
programmable arbitrary pulse template
Supports T1.102 line monitor
Transmit line short-circuit detection and protection
Separate Transmit and Receive Jitter Attenuators (2 per link)
Indicates the interval between the write pointer and the read pointer
of the FIFO in JA
Loss of signal indication with programmable thresholds according
to ITUT-T G.775, ETS 300 233 (E1) and ANSI T1.403 (T1/J1)
Supports Analog Loopback, Digital Loopback and Remote Loop-
back
The receiver and transmitter can be individually powered down
The device can be configured as T1, E1 or J1
Frame alignment/generation for T1 (per ITU-T G.704, TA-TSY-
000278, TR-TSY-000008), E1 (per ITU-T G.704), J1 (per JT G.704)
and un-framed mode
Supports T1/J1 Super Frame and Extended Super Frame, T1 Digi-
tal Multiplexer and Switch Line Carrier - 96, E1 CRC Multi-frame
and Signaling Multi-frame
Signaling extraction/insertion for CAS and RBS signaling
Provides programmable system interface supporting Mitel
bus, AT&T
1.544 Mb/s or 2.048 Mb/s non-multiplexed bus
Three HDLC controllers with separate 128-byte transmit and
receive FIFOs per controller
Programmable bit insertion and bit inversion on per channel/
timeslot basis
Provides Bit Oriented Message (BOM) generation and detection
Provides Automatic Performance Report Message (APRM) genera-
tion
Detects and generates alarms (AIS, RAI)
Provides performance monitor to count Bipolar Violation error,
Excess Zero error, CRC error, framing bit error, far end CRC error,
out of frame and change of framing alignment position
TM
CHI and MVIP bus, 8.192 Mb/s multiplexed bus and
Single T1/E1/J1 Long Haul /
Short Haul Transceiver
TM
ST-
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CONTROL INTERFACE
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GENERAL
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APPLICATIONS
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Supports System Loopback, Payload Loopback, Digital Loopback
and Inband Loopback
Detects and generates selectable PRBS and QRSS
Transmission and Extraction of Synchronization Supply Message
(SSM) in BITS application
Supports Serial Peripheral Interface (SPI) microprocessor and par-
allel Intel/Motorola non-multiplexed microprocessor interface
Global hardware and software reset
One general purpose I/O pin
Device power down
Flexible reference clock (N x 1.544 MHz or N x 2.048 MHz)
(0<N<5)
JTAG boundary scan
3.3 V I/O with 5 V tolerant inputs
Low power consumption (Typical 190 mW)
3.3 V and 1.8 V power supply
80-pin TQFP package
C.O, PABX, ISDN PRI
Wireless Base Stations
T1/E1/J1 ATM Gateways, Multiplexer
T1/E1/J1 Access Networks
LAN/WAN Router
Digital Cross Connect
SONET/SDH Add/Drop Equipment
Clock recovery at 1.544 MHz / 2.048 MHz for BITS application with
SSM support
IDT82P2281
August 20, 2009
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