82P2281PFG8 IDT, Integrated Device Technology Inc, 82P2281PFG8 Datasheet - Page 68

• Manufacturer Part Number: 82P2281PFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
BOFF[2:0] bits and the TSOFF[6:0] bits are not ‘0’ respectively.
the corresponding frame output on the RSD/MRSD pin will delay ‘N’
clock cycles to the framing pulse on the RSFS/MRSFS pin. (Here ‘N’ is
defined by the BOFF[2:0] bits.) When the CMS bit is ‘0’ and the
TSOFF[6:0] bits are set, the start of the corresponding frame output on
the RSD/MRSD pin will delay ‘8 x M’ clock cycles to the framing pulse on
the RSFS/MRSFS pin. (Here ‘M’ is defined by the TSOFF[6:0].)
Functional Description
The bit offset and channel offset are configured when the
When the CMS bit is ‘0’ and the BOFF[2:0] bits are set, the start of
Receive Clock Slave mode / Receive Multiplexed mode:
Receive Clock Master mode:
Receive Clock Master mode:
Receive Clock Slave mode / Receive Multiplexed mode:
RSD / MRSD
RSFS / MRSFS
RSCK / MRSCK
RSD / MRSD
RSFS / MRSFS
RSCK / MRSCK
RSFS / MRSFS
RSCK / MRSCK
RSD / MRSD
RSFS / MRSFS
RSCK / MRSCK
RSD / MRSD
Figure 23. No Offset When FE = 0 & DE = 1 In Receive Path
Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path
FE = 1, DE = 0
FE = 0, DE = 1
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
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SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
BOFF[2:0] bits are set, the start of the corresponding frame output on
the RSD/MRSD pin will delay ‘2 x N’ clock cycles to the framing pulse on
the RSFS/MRSFS pin. (Here ‘N’ is defined by the BOFF[2:0] bits.) When
the CMS bit is ‘1’ (i.e., in double clock mode) and the TSOFF[6:0] bits
are set, the start of the corresponding frame output on the RSD/MRSD
pin will delay ‘16 x M’ clock cycles to the framing pulse on the RSFS/
MRSFS pin. (Here ‘M’ is defined by the TSOFF[6:0].)
When the CMS bit is ‘1’ (i.e., in double clock mode) and the
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
August 20, 2009