82P2281PFG8 IDT, Integrated Device Technology Inc, 82P2281PFG8 Datasheet - Page 81

• Manufacturer Part Number: 82P2281PFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

Table 48: Control Over E Bits
3.20.1.2
CRC-4 Multi-Frame and Channel Associated Signaling (CAS) Multi-
Frame. The Frame Generator can also transmit alarm indication signal
when special conditions occurs in the received data stream. Interna-
tional bits, National bits and Extra bits replacements and data inversions
are all supported in the Frame Generator.
Associated Signaling (CAS) Multi-Frame are controlled by the FDIS bit,
the GENCRC bit, the CRCM bit and the SIGEN bit. Refer to Table 47 for
details.
Sequence (FAS) (‘0011011’) will replace the Bit 2 ~ Bit 8 of TS0 of each
even frame; the NFAS bit (‘1’) will replace the Bit 2 of TS0 of each odd
frame. If the FAS1INV bit is set, one FAS bit will be inverted; if the
SaX[1:4] bits will be transmitted in the Sa bit position if enabled by the
corresponding SaXEN bit (‘X’ is from 4 to 8).
on the base of the Basic frame generation. When it is generated, the
Signaling Multi-Frame alignment pattern (‘0000’) will replace the high
nibble (Bit 1 ~ Bit 4) of TS16 of every 16 Basic frames. If the CASPINV
bit is set, one 4-bit Signaling Multi-Frame alignment pattern will be
inverted.
the value set in the FGEN Extra register will be inserted into the Extra
bits (the Bit 5, 7 & 8 of TS16 of Frame 0 of the Signaling Multi-Frame).
MFAIS bit will be continuously transmitted in the Y bit position (the Bit 6
of TS16 of Frame 0 of the Signaling Multi-Frame).
IDT82P2281
Table 47: E1 Frame Generation
FEBEDIS OOCMFV
Basic Frame
CRC Multi-Frame
Modified CRC Multi-Frame
Channel Associated Signaling (CAS) Multi-
Frame
0
0
1
1
In E1 mode, the Frame Generator can generate Basic Frame,
The generation of the Basic frame, CRC Multi-Frame and Channel
When the Basic frame is generated, the Frame Alignment
When the CRC Multi-Frame is generated, the setting in the
The Channel Associated Signaling (CAS) Multi-Frame is generated
When the Signaling Multi-Frame is generated, if the XDIS bit is ‘0’,
When the Signaling Multi-Frame is generated, the value in the
Desired Frame Type
E1 Mode
X
X
0
1
SiDIS
X
X
0
1
A single zero is inserted into the E bit when a CRC-4 Error event is detected in the receive path. (the E1 bit corresponds to SMFI
and the E2 bit corresponds to SMFII)
The value in the Si[1] bit is inserted into the E1 bit position. The value in the Si[0] bit is inserted into the E2 bit position.
The value in the Si[1] bit is inserted into the E1 bit position. The value in the Si[0] bit is inserted into the E2 bit position.
The E bit positions are unchanged.
FDIS GENCRC CRCM SIGEN
0
0
0
0
0
0
0
1
1
1
0
1
X
X
0
0
1
0
X
X
X
X
1
1
81
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
FASALLINV bit is set, one 7-bit FAS pattern will be inverted; if the NFAS-
INV bit is set, one NFAS bit will be inverted.
set in the Si[1] and Si[0] bits will replace the International bit (Bit 1) of
FAS frame and NFAS frame respectively.
(RAI) can be transmitted as logic 1 in the A bit position. It is transmitted
manually when the REMAIS bit is ‘1’. It can also be transmitted automat-
ically when the AUTOYELLOW bit is set to ‘1’. In this case, the RAI
transmission criteria are selected by the G706RAI bit.
be transmitted in the Sa bit position if enabled by the corresponding
SaXEN bit (‘X’ is from 4 to 8).
generation. When it is generated, the CRC Multi-Frame alignment pat-
tern (‘001011’) will replace the Bit 1 of TS0 of the first 6 odd frames; the
calculated 4-bit CRC of the previous Sub-Multi-Frame will be inserted in
the CRC-bit positions of the current Sub-Multi-Frame. The CRC-bit posi-
tion is the Bit 1 of TS0 of each even frame. Refer to Table 18 for the
CRC Multi-Frame structure. If the CRCPINV bit is set, one 6-bit CRC
Multi-Frame alignment pattern will be inverted; if the CRCINV bit is set,
all 4 calculated CRC bits in one Sub-Multi-Frame will be inverted.
positions have been occupied by the CRC Multi-Frame alignment pat-
tern and CRC-4 checking bits, the remaining 2 International bit positions
are inserted by the E bits. The control over the E bits is illustrated in
Table 48.
can be overwritten by all ‘Zero’s or all ’One’s by setting the TS16LOS bit
or the TS16AIS bit respectively. The all zeros overwritten takes a higher
priority.
position and the calculated CRC-4 bit position can be changed. All the
other bits are transparently transmitted unless all ’One’s or all ‘Zero’s are
transmitted (refer to Chapter 3.20.6 All ‘Zero’s & All ‘One’s).
‘0’. If the FDIS bit is set to ‘1’, the data received from the Transmit Pay-
load Control will be transmitted transparently to the HDLC Transmitter.
When the Basic frame is generated, if the SiDIS bit is ‘0’, the value
When the Basic frame is generated, the Remote Alarm Indication
When the Basic frame is generated, the setting in the SaX[1] bit will
The CRC Multi-Frame is generated on the base of the Basic frame
When the CRC Multi-Frame is generated, since 14 International bit
When the Signaling Multi-Frame is generated, all the bits in TS16
When the Modified CRC Multi-Frame is generated, only the Sa bit
The frame can only be generated on the base of the FDIS bit being
E Bits Insertion
August 20, 2009