82P2281PFG8 IDT, Integrated Device Technology Inc, 82P2281PFG8 Datasheet - Page 69

• Manufacturer Part Number: 82P2281PFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the
channel offset can be configured from 0 to 127 channels (0 & 127 are
included).
3.17.1.5
configured by the TRI bit to be in high impedance state or to output the
processed data stream.
3.17.2.1
pin and framing pulse on the RSFS pin are used to output the data on
the RSD pin. The signaling bits on the RSIG pin are per-timeslot aligned
with the data on the RSD pin.
face is clocked by the RSCK. The active edge of the RSCK used to
update the pulse on the RSFS is determined by the FE bit. The active
edge of the RSCK used to update the data on the RSD and RSIG is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFS is ahead.
Basic frame, CRC Multi-frame, Signaling Multi-frame, or both the CRC
Multi-frame and Signaling Multi-frame, or the TS1 and TS 16 overhead.
All the indications are selected by the OHD bit, the SMFS bit and the
CMFS bit. The active polarity of the RSFS is selected by the FSINV bit.
Clock Master Full E1 mode and Receive Clock Master Fractional E1
mode.
Functional Description
Table 40: Operating Modes Selection In E1 Receive Path
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
RMUX RMODE
0
1
In Non-multiplexed mode, the channel offset can be configured
The output on the RSD/MRSD and the RSIG/MRSIG pins can be
In the Receive Clock Master mode, the timing signal on the RSCK
In the Receive Clock Master mode, the data on the system inter-
In the Receive Clock Master mode, the RSFS can indicate the
The Receive Clock Master mode includes two sub-modes: Receive
X
0
1
Output On RSD/MRSD & RSIG/MRSIG
Receive Clock Master Mode
not both 0s
G56K, GAP
00
X
X
1
Receive Clock Master Full E1
Receive Clock Master Fractional E1
Receive Clock Slave
Receive Multiplexed
Operating Mode
MRSCK, MRSFS
69
RSCK, RSFS
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.17.2
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
RSD pin is used to output the received data at the bit rate of 2.048 Mb/s.
While in the Multiplexed Mode, the received data from the link is byte
interleaved to form one high speed data stream and output on the
MRSD pin at the bit rate of 8.192 Mb/s.
receive system interface is in Receive Clcok Slave mode, otherwise if
the device outputs clock to RSCK from itself, the receive system inter-
face is in Receive Clcok Master mode.
the entire E1 frame, the Receive System Interface is in Receive Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on RSCK, the Receive System Interface is in Receive Clock
Master Fractional E1 mode.
various operating modes and the pins’ direction of the receive system
interface in different operating modes.
3.17.2.1.1
Master mode, the special feature in this mode is that the RSCK is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame is clocked out by the RSCK.
3.17.2.1.2
Master mode, the special feature in this mode is that the RSCK is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
selecting the G56K & GAP bits in the Receive Payload Control. The data
in the corresponding gapped duration is a don't care condition.
3.17.2.2
pin and framing pulse on the RSFS pin to output the data on the RSD
pin are provided by the system side. The signaling bits on the RSIG pin
are per-timeslot aligned with the data on the RSD pin.
is clocked by the RSCK. The active edge of the RSCK used to sample
Input
X
In E1 mode, the Receive System Interface can be set in Non-multi-
In the Non-multiplexed mode, if the RSCK is from outside, the
In the Receive Clock Master mode, if RSCK outputs pulses during
Table 40 summarizes how to set the receive system interface into
Besides all the common functions described in the Receive Clock
Besides all the common functions described in the Receive Clock
The RSCK is gapped during the timeslots or the Bit 8 duration by
In the Receive Clock Slave mode, the timing signal on the RSCK
In the Receive Clock Slave mode, the data on the system interface
E1 MODE
Receive Clock Slave Mode
Receive Clock Master Full E1 Mode
Receive Clock Master Fractional E1 Mode
Receive System Interface Pin
RSCK, RSFS, RSD, RSIG
MRSD, MRSIG
RSD, RSIG
Output
August 20, 2009