CY7C955-NC Cypress Semiconductor Corp, CY7C955-NC Datasheet - Page 10

• Manufacturer Part Number: CY7C955-NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C955-NC

• Lead Free Status / RoHS Status: Not Compliant

Transmit SONET Line Overhead Processor (TLOP)
The Transmit SONET line overhead processor (TLOP) pro-
vides BIP 8/24 generation and line level alarms.
The BIP 8/24 code is calculated as if the STS 3c frame was
composed of three STS 1s. The first B2 byte is calculated over
the first STS 1 frame, the second B2 byte over the second
STS 1 frame and the third B2 byte over the third STS 1 frame.
Each B2 bit is calculated over the line and SPE portions of the
previous frame before scrambling using even parity and insert-
ed into the current frame before scrambling. For STS 1 RATE,
a BIP 8 is calculated over the entire SPE and line overhead
and placed in B2.
The Line Alarm Indication Signal (LAIS), is asserted by chang-
ing all bits of the SONET frame into 1 before scrambling. LAIS
generation is controlled by a register setting (Reg 14H, bit 0).
The Line Far End Receive Failure (LFERF), also called Line
RDI, is indicated by placing a 110 pattern in bits 6,7, and 8 of
the first K2 byte. LFERF can be asserted under register
(Reg 20H, bit 0) control.
The Line Far End Block Errors (LFEBE) are located in the third
Z2 byte and indicate the number of B2 errors in the previous
frame interval. Legal values for this byte are 00h through 18h.
All bytes of the line data communication channel (D4 D12)
and all other unused bytes are encoded to 00h.
Transmit SONET Section Overhead Processor (TSOP)
The Transmit SONET Line Overhead Processor (TSOP) pro-
vides A1,A2 framing pattern generation, section BIP 8 (B1)
insertion, section level alarm insertion, and frame scrambling.
The A1 and A2 bytes provide a framing pattern for frame align-
ment. All A1 bytes are coded to F6h and all A2 bytes are coded
to 28h. These bytes are not scrambled upon transmission.
The STS 1 identification bytes, C1, are used for framing and
de-interleaving purposes and are coded the order in their ap-
pearance in the STS 3c frame. The first C1 byte is coded to
01h, the second to 02h, and the third to 03h.
The section BIP 8 (B1) is the byte-interleaved parity-8 calcu-
lated over all bytes of the previous frame after scrambling and
inserted into the current frame before scrambling.
The bytes of the section data communication channel, D1 D3
and the remaining unused bytes are set to 00h.
The frame is scrambled prior to transmission with the generat-
ing polynomial x
scrambled. The scrambler runs continuously through the
frame and resets at the beginning of the next transmission
frame. The scrambler may be optionally disabled.
Transmit Clock Generator (TCG)
The TCG accepts a byte-rate transmit clock from TRCLK that
operates at either 19.44 MHz for STS 3c/STM 1 RATE or at
6.48 MHz for STS 1 RATE. The Transmit PLL multiplies this
byte-rate reference by eight to produce the bit-rate clock used
by the parallel-to-serial converter. Optionally a bit-rate source
can be taken from an external source (TBYP = 1) or from the
Receive Clock Recovery block when in loop-time mode
(LOOPT = 1). In loop-time mode the recovered clock is used
to provide timing to the transmitter.
7
+ x
6
+ 1. The A1, A2, and C1 bytes are not
PRELIMINARY
10
Parallel to Serial Converter (PSC)
The PSC converts the parallel data from the TSOP to serial
data. The bit rate clock is derived from the Transmit Clock Gen-
erator. The serialized data and aligned output clock are pre-
sented to the Transmit Output Multiplexer.
Transmit Output Multiplexer (TOM)
The TOM selects between the serialized output data stream
and associated clock provided by the PSC and the recovered
data and clock from the Receive Clock Recovery block for
transmission based on the state of the local loop back enable
(LLE) register (Reg 05H, bit 2). When LLE = 1 the recovered
data and recovered clock is selected for output on the transmit
data lines (TXD ) and the transmit clock lines (TXC ). The
output signal is 100K compatible differential Positive-refer-
enced ECL (PECL) signal capable of driving any copper or
fiber based media with impedances as LOW as 50 .
Receive Section
Receive Clock Recovery (RCR)
The RCR provides clock and data recovery from an incoming
differential PECL data stream. Clock and data are recovered
from the incoming differential PECL data stream without the
need for external buffering and AC-coupling. The built-in line
receiver inputs have a wide common-mode range (2.5 5V)
and the ability to receive signals with as little as 200 mV differ-
ential voltage. They are compatible with all PECL signals. They
are compatible with all PECL signals driven by optical modules
or twisted-pair equalizers. The Receive PLL uses the RRCLK
as a byte-rate reference. This input is multiplied by 8 and is
used to improve PLL lock time and to provide a center frequen-
cy for operation in the absence of input data stream transitions.
The receiver can recover clock and data in two different fre-
quency ranges depending on the state of the RATE0 pin. To
insure accurate data and clock recovery, the received data
stream must be within 1000 ppm of RRCLK * 8 (The PLL will
declare Out Of Lock if the data rate is different from REFCLK
x 8 by more than 2000 ppm. The PLL will remain Out Of Lock
until the data rate pulls back to within 700 ppm of REFCLK x
8 frequency). The standards, however, specify that the
RRCLK*8 frequency accuracy be within 20 100 ppm. The wid-
er frequency tolerance range of the CY7C955 is an advantage
that allows for higher frequency tolerance in bench testing set-
ups.
A Loss of Signal (ROOLV = 1) is declared when no transitions
have been detected on the incoming data stream for more than
512 bit-times. LOS is cleared when two valid framing patterns
(A1, A2) have been found and the intervening data does not
contain a period that violates the minimum transitions limit.
Serial to Parallel Conversion (SPC)
The SPC converts bit serial data to byte serial data from either
the recovered received data or the transmit data from the PSC
depending on the state of the DLE register (Reg 05H, bit 1).
When DLE =1 transmit data is used for serial to parallel con-
version. The SPC also provides SONET framing by scanning
the incoming data for the SONET framing pattern A1, A2. For
STS 1 RATE the framer looks for the pattern F628h and for
STS 3
F6F6F6282828h. Out of Frame (OOF) is declared when four
consecutive frames contain a framing error. OOF clears when
two frames contain valid framing characters. Loss of Frame
RATE
the
framer
looks
for
CY7C955
the
pattern