CY7C955-NC Cypress Semiconductor Corp, CY7C955-NC Datasheet - Page 72

• Manufacturer Part Number: CY7C955-NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C955-NC

• Lead Free Status / RoHS Status: Not Compliant

Functional Timing Diagram
Timing Modes
Figure 12, 13, and 14 shows how to connect the clock refer-
ence for different applications.
In the presence of a 155.52 MHz/51.84 MHz primary reference
source (PRS). The configuration described in Figure 12 should
be used.
reference clock source provides the accurate bit synchroniza-
tion needed for the transmit data stream.
Input Data
TBYP is HIGH and RBYP is LOW. The primary
RXD±
Figure 12. Clock Synthesis
RXD±
CY7C955
19.44 MHz
TRCLK±
RRCLK±
Internal
Tx Clock
Source
(continued)
TCLK
Stratum or free-run
reference
PRELIMINARY
Figure 14. Conceptual Clocking Structure
B
A
Clock Synthesizer
72
Clock Recovery
If the application is a LAN termination equipment, the config-
uration described in Figure 13 should be used. LOOPT
(Reg–5H, bit 0) is HIGH to enable loop timing mode. In loop
timing mode, The clock recovered from the received data
stream is being used to synchronize the transmit datastream.
If that clock is lost, RRCLK x 8 will be used as the clock refer-
ence. The clocking architecture of the CY7C955 is shown in
Figure 14.
TRCLK±
RRCLK±
Input Data
/8
RXD±
Figure 13. Loop Timing
CY7C955
19.44 MHz
TRCLK±
RRCLK±
Internal
Rx Clock
Source
TCLK
TCLK
Stratum or free-run
reference
CY7C955