CY7C955-NC Cypress Semiconductor Corp, CY7C955-NC Datasheet - Page 8

• Manufacturer Part Number: CY7C955-NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C955-NC

• Lead Free Status / RoHS Status: Not Compliant

Description
Transmit Section
Transmit Utopia Interface (TUI)
The transmit interface provides a simple access from the ex-
ternal environment to the ATM Transceiver. The operation of
this interface is compliant with the Utopia interface specifica-
tion. The interface provides a 9-bit by 4-cell FIFO to decouple
the system interface from the ATM physical layer timing. 9-bit
words are clocked into the device through a clocked FIFO sys-
tem interface. These 9 bits include an 8-bit data word along
with a Start Of Cell (SOC) indication. The interface also pro-
vides full and almost full indications (TCA). Maximum clock
rate for this interface is 33 MHz.
Transmit ATM Cell Processor (TACP)
The ATM cell processor provides HEC generation, idle/unas-
signed cell header modification, payload scrambling, and GFC
insertion.
HEC Generator
The Header Error Check (HEC) code is contained in the last
byte of the ATM cell header and is capable of single error cor-
rection and multiple error detection. When optionally generat-
ed, the Transmit ATM Cell Processor calculates a CRC 8 over
the first four bytes of the ATM cell header using the polynomial
x
to the residue of this function. The HEC is calculated in accor-
dance with ANSI T1.624 1993 and CCITT Recommendation
I.432. This HEC sequence is placed in the 5th byte of the ATM
cell header.
Idle/Unassigned Cell Header Modification
Idle (Unassigned) cells are sent by the ATM cell processor
whenever a complete cell is not contained within the Transmit
FIFO. This transforms the non-continuous cell input stream
into a continuous stream of assigned and unassigned cells.
The ATM cell processor provides the ability to overwrite the
Generic Flow Control (GFC), the Payload Type Indication
(PTI), and the Cell Loss Priority (CLP) fields of Idle (Unas-
signed) cells with the values contained in the corresponding
configuration registers. VPI and VCI are set to zero in Idle (Un-
assigned) cells.
Payload Scrambler
The 48 bytes of the ATM payload are scrambled using a par-
allel implementation of the polynomial x
CCITT Recommendation I.432. The scrambler can be option-
ally deselected.
GFC Insertion
The transmitted GFC field of an ATM cell can be derived from
different sources. For assigned cells, the default is from pins
TDAT[7:0]. For Idle (Unassigned) cells, the default is from
GFC[3:0] (Reg 61H, bit 7 bit 4). However, if any bit of
TGFCE[3:0] (Reg 67H, bit 7 bit4) is set, the corresponding
transmitted GFC location will instead be taken from the serial
TGFC (pin 52) input following the functional timing specifica-
tions described in the section on Transmit GFC Serial Link
Interface.
8
+ x
2
+ x + 1. The coset x
6
+ x
4
+ x
2
+ 1 is added (modulo 2)
43
PRELIMINARY
+ 1 as described in
8
Transmit SONET Path Overhead Processor (TPOP)
The SONET path overhead processor provides payload point-
er alignment (H1, H2), path overhead insertion, and insertion
of the Synchronous Payload Envelope (SPE). ATM cells (both
assigned and unassigned) are inserted into the SPE for trans-
mission in the SONET frame
SONET Overhead Insertion
The SONET/SDH STS 3c/STM 1 frame structure is shown in
Figure 1 and the SONET STS 1 frame structure is shown in
Figure 2. The SONET frame occurs once every 125 s and is
transmitted beginning with the A1 bytes, followed by the A2
bytes, C1 bytes, 261 bytes (87 bytes for STS 1) of the Syn-
chronous Payload Envelope (SPE), B1 bytes, etc., until the
entire frame is transmitted.
The TPOP generates the H1 and H2 bytes that indicate the
beginning of the SPE and the H4 byte that indicates the ATM
cell offset within the SPE. The default initial value for H1 and
H2 pointer is 522, meaning that the first byte of the SPE (J1)
corresponding to a frame actually starts after the C1 byte of
the next frame.
In the default case described above, a 6h is present in the New
Data Flag (NDF) portion of the first H1 (bits 0 4), a 2h is
present in bits 5 7 and a 0Ah is present in the first H2 byte.
The remaining H1 bytes for STS 3c/STM 1 are set to 93h and
the remaining H2 bytes are set to FFh which is the concatena-
tion indication for the J1 pointer. The Pointer Action byte, H3,
is set to 00h. During Path AIS all of the H1 and H2 bits are set
to 1.
The STS path trace J1 is set to all zeros. The path BIP 8 (B3)
byte provides path error monitoring. This function calculates
the bit-interleaved parity-8 code using even parity over the pre-
vious SPE before scrambling and is inserted into the current
B3 byte before scrambling. Bit-interleaved parity-8 forces the
number of 1s in the xth bit of every byte in the previous SPE
plus the xth bit of the B3 byte in the current SPE to be an even
number.
The path signal level indicator, C2, defaults to 13h.
The path status, G1, has several functions. Bits 1 through 4
are used to indicate Far End Block Errors (FEBE) derived by
counting the number of BIP 8 errors occurred in the last frame
received. Valid codes are 0 through 8. If more than 8 errors
have accumulated since the last, frame the maximum value is
sent with the current frame, the FEBE counter is decremented
by 8, and the remaining errors are sent with the next frame.
FEBE may be inserted through register control for diagnostic
purposes. Bits 1 through 4 can also be used to transmit Far
End Receive Failures by setting these bits to 9 (1001). This
error indicates to the far end that cell delineation has been lost.
Bit 5 can be used to generate a yellow alarm condition. The
default value for this bit is 0 (no alarm).
The multi-frame indicator, H4, is used to indicate the first ATM
cell and may take on values of 00 to 34h.
The remaining bytes, F2, Z3, Z4, and Z5, are not used by the
SONET path processing and are set to 00h upon transmission.
When operating in STS 1 mode, SPE columns 30 and 59 can
be configured as fixed stuff columns.
CY7C955