S2068TB Applied Micro Circuits Corporation, S2068TB Datasheet - Page 6

• Manufacturer Part Number: S2068TB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S2068TB

• Number Of Receivers: 2
• Protocols Supported: IEEE 802.3z
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.47V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

The TBC must be frequency locked to REFCLK, but
may have an arbitrary but fixed phase relationship.
Adjustment of internal timing of the S2068 is per-
formed during reset. Once synchronized, the S2068
can tolerate up to 3ns of phase drift between TBC
and REFCLK.
Figure 5 demonstrates the flexibility afforded by the
S2068. A low jitter reference is provided directly to
the S2068 at either 1/10 or 1/20 the serial data rate.
This insures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. This clock can be buffered as re-
quired without concern about added delay. There is
no phase requirement placed upon TCLKO and the
TBCx clock, which is provided back to the S2068,
other than that they remain within
relationship established at reset.
The S2068 also supports the traditional REFCLK
clocking found in many Gigabit Ethernet applications
and is illustrated in Figure 6.
Half Rate Operation
The S2068 supports full and half rate operation for
Table 3. Data to 8B/10B Alphabetic Representation
Figure 6. GE DIN Clocking with REFCLK
6
S2068
I D
8
[ N
B
: 0
1 /
] 9
0
B
r o
a
ASIC
p l
MAC
D
O
. h
U
e r
[ T
p
: 0
. r
] 9
0
a
1
b
2
c
3
d
TCLKO
DINx[0:9]
TBCx
D
a
4
e
a t
OSCILLATOR
125 MHz
3ns of the phase
S2068
B
REFCLK
5
y
i
REF
PLL
e t
6
f
7
g
8
h
9
j
DUAL GIGABIT ETHERNET TRANSCEIVER
all modes of operation. When RATE is LOW, the
S2068 serial data rate equals the VCO frequency.
When RATE is HIGH, the VCO is divided by two
before being provided to the chip. Thus, the S2068
can support Gigabit Ethernet and serial backplane
functions at full and half the VCO rate.
Parallel to Serial Conversion
The 10-bit parallel data handled by the S2068 device
should be from a DC-balanced encoding scheme,
such as the 8B/10B transmission code, in which in-
formation to be transmitted is encoded, 8 bits at a
time, into a 10-bit transmission character and must
be compliant with IEEE 802.3z Gigabit Ethernet.
The 8B/10B transmission code includes serial en-
coding and decoding rules, special characters, and
error control. Information is encoded, 8 bits at a time,
into a 10 bit transmission character. The characters
defined by this code ensure that short run lengths
and enough transitions are present in the serial bit
stream to make clock recovery possible at the re-
ceiver. The encoding also greatly increases the like-
lihood of detecting any single or multiple errors that
might occur during the transmission and reception of
data
Table 3 identifies the mapping of the 8B/10B charac-
ters to the data inputs of the S2068. The S2068 will
serialize the parallel data for each channel and will
transmit bit “a” or DIN[0] first.
Frequency Synthesizer (PLL)
The S2068 synthesizes a serial transmit clock from
the reference signal provided. The S2068 will obtain
phase and frequency lock within 2500 bit times after
the start of receiving reference clock inputs. Reliable
locking of the transmit PLL is assured, but a lock-
detect output is NOT provided.
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to insure
that the clock recovery units can lock to the serial
data.
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
1
.
October 13, 2000 / Revision D