DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 27

• Manufacturer Part Number: DJLXT972ALC.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT972ALC.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.4.2
5.4.2.1
5.4.2.2
5.4.3
Cortina Systems
On power-up or hardware reset, the LXT972A PHY reads the Hardware Control Interface
pins and sets the MDIO registers accordingly.
When the network link is forced to a specific configuration, the LXT972A PHY immediately
begins operating the network interface as commanded. When auto-negotiation is enabled,
the LXT972A PHY begins the auto-negotiation/parallel-detection operation.
Reduced-Power Modes
This section discusses the LXT972A PHY reduced-power modes.
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is
High, the following conditions are true:
Software Power Down
Software power-down control is provided by register bit 0.11 in the Control Register.
During soft power-down, the following conditions are true:
Reset
The LXT972A PHY provides both hardware and software resets, each of which manage
differently the configuration control of auto-negotiation, speed, and duplex-mode
selection.
For a software reset, register bit 0.15 = 1. For register bit definitions used for software
reset, see
®
• Force network link operation to:
• Allow auto-negotiation/parallel-detection
• The LXT972A PHY network port and clock are shut down.
• All outputs are tristated.
• All weak pad pull-up and pull-down resistors are disabled.
• The MDIO registers are not accessible.
• The network port is shut down.
• The MDIO registers remain accessible.
• During a software reset, bit settings in
• During a software reset, registers are available for reading. To see when the LXT972A
LXT972A Single-Port 10/100 Mbps PHY Transceiver
— 100BASE-TX, Full-Duplex
— 100BASE-TX, Half-Duplex
— 10BASE-T, Full-Duplex
— 10BASE-T, Half-Duplex
Register - Address 4, Hex 4, on page 67
configuration pins. Instead, the bit settings revert to the values that were read in
during the last hardware reset. Therefore, any changes to pin values made since the
last hardware reset are not detected during a software reset.
PHY has completed reset, the reset bit can be polled (that is, register bit 0.15 = 0).
Table 39, Control Register - Address 0, Hex 0, on page
Table 43, Auto-Negotiation Advertisement
are not re-read from the LXT972A PHY
64.
5.4 Initialization
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