DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 57

• Manufacturer Part Number: DJLXT972ALC.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT972ALC.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
Table 31
Figure 24
Cortina Systems
10BASE-T Receive Timing Parameters
10BASE-T Transmit Timing
®
RXD, RX_DV, RX_ER Setup to
RX_CLK High
RXD, RX_DV, RX_ER Hold from
RX_CLK High
TPIP/N in to RXD out (Rx latency)
CRS asserted to RXD, RX_DV,
RX_ER asserted
RXD, RX_DV, RX_ER de-asserted to
CRS de-asserted
TPI in to CRS asserted
TPI quiet to CRS de-asserted
TPI in to COL asserted
TPI quiet to COL de-asserted
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
LXT972A Single-Port 10/100 Mbps PHY Transceiver
TX_EN,
TX_ER
TX_CLK
testing.
rate. 10BASE-T bit time = 10
TXD,
CRS
TPO
Parameter
t
1
t
3
-7
s or 100 ns.
t
5
Sym
t1
t2
t3
t4
t5
t6
t7
t8
t9
Min
4.2
0.3
10
10
5
2
6
1
5
Typ
t
–
–
–
–
–
–
–
–
–
2
1
Max
6.6
0.5
32
28
10
31
10
–
–
7.2 AC Timing Diagrams and
t
4
Units
BT
BT
BT
BT
BT
BT
BT
ns
ns
2
Test Conditions
B3460-01
Parameters
–
–
–
–
–
–
–
–
–
Page 57