DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 34

• Manufacturer Part Number: DJLXT972ALC.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT972ALC.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
Figure 10
5.6.7.1
5.6.7.2
Note:
Cortina Systems
Loopback Paths
Operational Loopback
Internal Digital Loopback (Test Loopback)
A test loopback function is provided for diagnostic testing of the LXT972A PHY. During
test loopback, twisted-pair interfaces are disabled. Data transmitted by the MAC is
internally looped back by the LXT972A PHY and returned to the MAC.
Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled
by setting the following register bits:
Parallel detection can resolve the PHY configuration.
®
• Operational loopback is provided for 10 Mbps half-duplex links when register bit 16.8
• Operational loopback is not provided for 100 Mbps links, full-duplex links, or when
• register bit 0.14 = 1 (Setting to enable loopback mode)
• register bit 0.8 = 1 (Setting for full-duplex mode)
• register bit 0.12 = 0 (Disable auto-negotiation)
LXT972A Single-Port 10/100 Mbps PHY Transceiver
= 0. Data that the MAC (TXData) transmits loops back on the receive side of the MII
(RXData).
Register 16.8 = 1.
MII
LXT97x PHY
Loopback
Operational
Loopback
10T
Digital
Block
Test Loopback
Loopback
100X
Analog
Block
5.6 MII Operation
B3393-02
Driver
TX
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