DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 62
DJLXT972ALC.A4
Manufacturer Part Number
DJLXT972ALC.A4
Description
Manufacturer
Cortina Systems Inc
Datasheet
1.DJLXT972ALC.A4.pdf
(80 pages)
Specifications of DJLXT972ALC.A4
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LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
Table 37
Cortina Systems
RESET_L Pulse Width and Recovery Timing
®
RESET_L pulse width
RESET_L recovery
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
LXT972A Single-Port 10/100 Mbps PHY Transceiver
testing.
performance. The PHY comes out of reset after a delay of no more than 300 μ s. System designers should
consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than
300 μ s before accessing the MDIO port.
Parameter
delay2
Symbol
t1
t2
Min
10
–
Typ
–
1
Max
300
–
Units
7.2 AC Timing Diagrams and
ns
μ s
Test Conditions
–
–
Parameters
Page 62
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